board/gen860t/gen860t.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * Keith Outwater, keith_outwater@mvis.com
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <virtex2.h>
  26 #include <common.h>
  27 #include <mpc8xx.h>
  28 #include <asm/8xx_immap.h>
  29 #include "beeper.h"
  30 #include "fpga.h"
  31 #include "ioport.h"
  32
  33 #ifdef CONFIG_STATUS_LED
  34 #include <status_led.h>
  35 #endif
  36
  37 #if defined(CFG_CMD_MII) && defined(CONFIG_MII)
  38 #include <net.h>
  39 #endif
  40
  41 #if 0
  42 #define GEN860T_DEBUG
  43 #endif
  44
  45 #ifdef GEN860T_DEBUG
  46 #define PRINTF(fmt,args...)     printf (fmt ,##args)
  47 #else
  48 #define PRINTF(fmt,args...)
  49 #endif
  50
  51 /*
  52  * The following UPM init tables were generated automatically by
  53  * Motorola's MCUINIT program. See the README file for UPM to
  54  * SDRAM pin assignments if you want to type this data into
  55  * MCUINIT in order to reverse engineer the waveforms.
  56  */
  57
  58 /*
  59  * UPM initialization tables for MICRON MT48LC16M16A2TG SDRAM devices
  60  * (UPMA) and Virtex FPGA SelectMap interface (UPMB).
  61  * NOTE that unused areas of the table are used to hold NOP, precharge
  62  * and mode register set sequences.
  63  *
  64  */
  65 #define UPMA_NOP_ADDR                   0x5
  66 #define UPMA_PRECHARGE_ADDR             0x6
  67 #define UPMA_MRS_ADDR                   0x12
  68
  69 #define UPM_SINGLE_READ_ADDR    0x00
  70 #define UPM_BURST_READ_ADDR             0x08
  71 #define UPM_SINGLE_WRITE_ADDR   0x18
  72 #define UPM_BURST_WRITE_ADDR    0x20
  73 #define UPM_REFRESH_ADDR                0x30
  74
  75 const uint sdram_upm_table[] = {
  76         /* single read   (offset 0x00 in upm ram) */
  77         0x0e0fdc04, 0x01adfc04, 0x0fbffc00, 0x1fff5c05,
  78         0xffffffff, 0x0fffffcd, 0x0fff0fce, 0xefcfffff,
  79         /* burst read    (offset 0x08 in upm ram) */
  80         0x0f0fdc04, 0x00fdfc04, 0xf0fffc00, 0xf0fffc00,
  81         0xf1fffc00, 0xfffffc00, 0xfffffc05, 0xffffffff,
  82         0xffffffff, 0xffffffff, 0x0ffffff4, 0x1f3d5ff4,
  83         0xfffffff4, 0xfffffff5, 0xffffffff, 0xffffffff,
  84         /* single write  (offset 0x18 in upm ram) */
  85         0x0f0fdc04, 0x00ad3c00, 0x1fff5c05, 0xffffffff,
  86         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  87         /* burst write   (offset 0x20 in upm ram) */
  88         0x0f0fdc00, 0x10fd7c00, 0xf0fffc00, 0xf0fffc00,
  89         0xf1fffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
  90         0xffffffff, 0xffffffff, 0xffffffff, 0xfffff7ff,
  91         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  92         /* refresh       (offset 0x30 in upm ram) */
  93         0x1ffddc84, 0xfffffc04, 0xfffffc04, 0xfffffc84,
  94         0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
  95         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  96         /* exception     (offset 0x3C in upm ram) */
  97    };
  98
  99 const uint selectmap_upm_table[] = {
 100         /* single read   (offset 0x00 in upm ram) */
 101         0x88fffc06, 0x00fff404, 0x00fffc04, 0x33fffc00,
 102         0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
 103         /* burst read    (offset 0x08 in upm ram) */
 104         0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
 105         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 106         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 107         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 108         /* single write  (offset 0x18 in upm ram) */
 109         0x88fffc04, 0x00fff400, 0x77fffc05, 0xffffffff,
 110         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 111         /* burst write   (offset 0x20 in upm ram) */
 112         0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
 113         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 114         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 115         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 116         /* refresh       (offset 0x30 in upm ram) */
 117         0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
 118         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 119         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 120         /* exception     (offset 0x3C in upm ram) */
 121         0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff
 122 };
 123
 124 /*
 125  * Check board identity.  Always successful (gives information only)
 126  */
 127 int
 128 checkboard(void)
 129 {
 130         DECLARE_GLOBAL_DATA_PTR;
 131
 132     unsigned char *s;
 133     unsigned char buf[64];
 134     int i;
 135
 136     i = getenv_r("board_id", buf, sizeof(buf));
 137     s = (i>0) ? buf : NULL;
 138
 139         if (s) {
 140                 printf("%s ", s);
 141         } else {
 142                 printf("<unknown> ");
 143         }
 144
 145     i = getenv_r("serial#", buf, sizeof(buf));
 146     s = (i>0) ? buf : NULL;
 147
 148         if (s) {
 149                 printf("S/N %s\n", s);
 150         } else {
 151                 printf("S/N <unknown>\n");
 152         }
 153
 154     printf("CPU at %s MHz, ",strmhz(buf, gd->cpu_clk));
 155         printf("local bus at %s MHz\n", strmhz(buf, gd->bus_clk));
 156     return (0);
 157 }
 158
 159 /*
 160  * Initialize SDRAM
 161  */
 162 long int
 163 initdram(int board_type)
 164 {
 165     volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
 166     volatile memctl8xx_t *memctl = &immr->im_memctl;
 167
 168     upmconfig(UPMA,
 169                           (uint *)sdram_upm_table,
 170                           sizeof(sdram_upm_table) / sizeof(uint)
 171                          );
 172
 173     /*
 174      * Setup MAMR register
 175      */
 176     memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
 177     memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
 178
 179     /*
 180      * Map CS1* to SDRAM bank
 181      */
 182     memctl->memc_or1 = CFG_OR1;
 183     memctl->memc_br1 = CFG_BR1;
 184
 185         /*
 186          * Perform SDRAM initialization sequence:
 187          * 1. Apply at least one NOP command
 188          * 2. 100 uS delay (JEDEC standard says 200 uS)
 189          * 3. Issue 4 precharge commands
 190          * 4. Perform two refresh cycles
 191          * 5. Program mode register
 192          *
 193          * Program SDRAM for standard operation, sequential burst, burst length
 194          * of 4, CAS latency of 2.
 195          */
 196     memctl->memc_mar = 0x00000000;
 197         memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
 198                                            MCR_MLCF(0) | UPMA_NOP_ADDR;
 199         udelay(200);
 200     memctl->memc_mar = 0x00000000;
 201         memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
 202                                            MCR_MLCF(4) | UPMA_PRECHARGE_ADDR;
 203
 204     memctl->memc_mar = 0x00000000;
 205         memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
 206                                            MCR_MLCF(2) | UPM_REFRESH_ADDR;
 207
 208     memctl->memc_mar = 0x00000088;
 209         memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
 210                                            MCR_MLCF(1) | UPMA_MRS_ADDR;
 211
 212     memctl->memc_mar = 0x00000000;
 213         memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
 214                                            MCR_MLCF(0) | UPMA_NOP_ADDR;
 215         /*
 216          * Enable refresh
 217          */
 218     memctl->memc_mamr |= MAMR_PTAE;
 219
 220     return (SDRAM_SIZE);
 221 }
 222
 223 /*
 224  * Disk On Chip (DOC) Millenium initialization.
 225  * The DOC lives in the CS2* space
 226  */
 227 #if (CONFIG_COMMANDS & CFG_CMD_DOC)
 228 extern void
 229 doc_probe(ulong physadr);
 230
 231 void
 232 doc_init(void)
 233 {
 234         printf("Probing at 0x%.8x: ", DOC_BASE);
 235         doc_probe(DOC_BASE);
 236 }
 237 #endif
 238
 239 /*
 240  * Miscellaneous intialization
 241  */
 242 int
 243 misc_init_r (void)
 244 {
 245     volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
 246     volatile memctl8xx_t *memctl = &immr->im_memctl;
 247
 248         /*
 249          * Set up UPMB to handle the Virtex FPGA SelectMap interface
 250          */
 251         upmconfig(UPMB, (uint *)selectmap_upm_table,
 252                           sizeof(selectmap_upm_table) / sizeof(uint));
 253
 254     memctl->memc_mbmr = 0x0;
 255
 256         config_mpc8xx_ioports(immr);
 257
 258 #if (CONFIG_COMMANDS & CFG_CMD_MII)
 259         mii_init();
 260 #endif
 261
 262 #if (CONFIG_FPGA)
 263         gen860t_init_fpga();
 264 #endif
 265         return 0;
 266 }
 267
 268 /*
 269  * Final init hook before entering command loop.
 270  */
 271 int
 272 last_stage_init(void)
 273 {
 274 #if !defined(CONFIG_SC)
 275         unsigned char buf[256];
 276         int i;
 277
 278         /*
 279          * Turn the beeper volume all the way down in case this is a warm boot.
 280          */
 281         set_beeper_volume(-64);
 282         init_beeper();
 283
 284         /*
 285          * Read the environment to see what to do with the beeper
 286          */
 287     i = getenv_r("beeper", buf, sizeof(buf));
 288         if (i > 0) {
 289                 do_beeper(buf);
 290         }
 291 #endif
 292         return 0;
 293 }
 294
 295 /*
 296  * Stub to make POST code happy.  Can't self-poweroff, so just hang.
 297  */
 298 void
 299 board_poweroff(void)
 300 {
 301         puts("### Please power off the board ###\n");
 302     while (1);
 303 }
 304
 305 #ifdef CONFIG_POST
 306 /*
 307  * Returns 1 if keys pressed to start the power-on long-running tests
 308  * Called from board_init_f().
 309  */
 310 int post_hotkeys_pressed(void)
 311 {
 312         return 0;       /* No hotkeys supported */
 313 }
 314 #endif
 315
 316 /* vim: set ts=4 sw=4 tw=78 : */