board/hymod/bsp.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  * hacked for Hymod FPGA support by Murray.Jensen@csiro.au, 29-Jan-01
  24  */
  25
  26 #include <common.h>
  27 #include <command.h>
  28 #include <net.h>
  29 #include <asm/iopin_8260.h>
  30 #include <cmd_bsp.h>
  31
  32 /*-----------------------------------------------------------------------
  33  * Board Special Commands: FPGA load/store, EEPROM erase
  34  */
  35
  36 #if (CONFIG_COMMANDS & CFG_CMD_BSP)
  37
  38 #define LOAD_SUCCESS            0
  39 #define LOAD_FAIL_NOCONF        1
  40 #define LOAD_FAIL_NOINIT        2
  41 #define LOAD_FAIL_NODONE        3
  42
  43 #define STORE_SUCCESS           0
  44
  45 /*
  46  * Programming the Hymod FPGAs
  47  *
  48  * The 8260 io port config table is set up so that the INIT pin is
  49  * held Low (Open Drain output 0) - this will delay the automatic
  50  * Power-On config until INIT is released (by making it an input).
  51  *
  52  * If the FPGA has been programmed before, then the assertion of PROGRAM
  53  * will initiate configuration (i.e. it begins clearing the RAM).
  54  *
  55  * When the FPGA is ready to receive configuration data (either after
  56  * releasing INIT after Power-On, or after asserting PROGRAM), it will
  57  * pull INIT high.
  58  *
  59  * Notes from Paul Dunn:
  60  *
  61  *  1. program pin should be forced low for >= 300ns
  62  *     (about 20 bus clock cycles minimum).
  63  *
  64  *  2. then wait for init to go high, which signals
  65  *     that the FPGA has cleared its internal memory
  66  *     and is ready to load
  67  *
  68  *  3. perform load writes of entire config file
  69  *
  70  *  4. wait for done to go high, which should be
  71  *     within a few bus clock cycles. If done has not
  72  *     gone high after reasonable period, then load
  73  *     has not worked (wait several ms?)
  74  */
  75
  76 int
  77 fpga_load (int mezz, uchar *addr, ulong size)
  78 {
  79         DECLARE_GLOBAL_DATA_PTR;
  80
  81         hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
  82         xlx_info_t *fp;
  83         xlx_iopins_t *fpgaio;
  84         volatile uchar *fpgabase;
  85         volatile uint cnt;
  86         uchar *eaddr = addr + size;
  87         int result;
  88
  89         if (mezz)
  90                 fp = &cp->mezz.xlx[0];
  91         else
  92                 fp = &cp->main.xlx[0];
  93
  94         if (!fp->mmap.prog.exists)
  95                 return (LOAD_FAIL_NOCONF);
  96
  97         fpgabase = (uchar *)fp->mmap.prog.base;
  98         fpgaio = &fp->iopins;
  99
 100         /* set enable HIGH if required */
 101         if (fpgaio->enable_pin.flag)
 102                 iopin_set_high (&fpgaio->enable_pin);
 103
 104         /* ensure INIT is released (set it to be an input) */
 105         iopin_set_in (&fpgaio->init_pin);
 106
 107         /* toggle PROG Low then High (will already be Low after Power-On) */
 108         iopin_set_low (&fpgaio->prog_pin);
 109         udelay (1);     /* minimum 300ns - 1usec should do it */
 110         iopin_set_high (&fpgaio->prog_pin);
 111
 112         /* wait for INIT High */
 113         cnt = 0;
 114         while (!iopin_is_high (&fpgaio->init_pin))
 115                 if (++cnt == 10000000) {
 116                         result = LOAD_FAIL_NOINIT;
 117                         goto done;
 118                 }
 119
 120         /* write configuration data */
 121         while (addr < eaddr)
 122                 *fpgabase = *addr++;
 123
 124         /* wait for DONE High */
 125         cnt = 0;
 126         while (!iopin_is_high (&fpgaio->done_pin))
 127                 if (++cnt == 100000000) {
 128                         result = LOAD_FAIL_NODONE;
 129                         goto done;
 130                 }
 131
 132         /* success */
 133         result = LOAD_SUCCESS;
 134
 135   done:
 136
 137         if (fpgaio->enable_pin.flag)
 138                 iopin_set_low (&fpgaio->enable_pin);
 139
 140         return (result);
 141 }
 142
 143 /* ------------------------------------------------------------------------- */
 144 int
 145 do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 146 {
 147         uchar *addr, *save_addr;
 148         ulong size;
 149         int mezz, arg, result;
 150
 151         switch (argc) {
 152
 153         case 0:
 154         case 1:
 155                 break;
 156
 157         case 2:
 158                 if (strcmp (argv[1], "info") == 0) {
 159                         printf ("\nHymod FPGA Info...\n");
 160                         printf ("\t\t\t\tAddress\t\tSize\n");
 161                         printf ("\tMain Configuration:\t0x%08x\t%d\n",
 162                                 FPGA_MAIN_CFG_BASE, FPGA_MAIN_CFG_SIZE);
 163                         printf ("\tMain Register:\t\t0x%08x\t%d\n",
 164                                 FPGA_MAIN_REG_BASE, FPGA_MAIN_REG_SIZE);
 165                         printf ("\tMain Port:\t\t0x%08x\t%d\n",
 166                                 FPGA_MAIN_PORT_BASE, FPGA_MAIN_PORT_SIZE);
 167                         printf ("\tMezz Configuration:\t0x%08x\t%d\n",
 168                                 FPGA_MEZZ_CFG_BASE, FPGA_MEZZ_CFG_SIZE);
 169                         return 0;
 170                 }
 171                 break;
 172
 173         case 3:
 174                 if (strcmp (argv[1], "store") == 0) {
 175                         addr = (uchar *) simple_strtoul (argv[2], NULL, 16);
 176
 177                         save_addr = addr;
 178 #if 0
 179                         /* fpga readback unimplemented */
 180                         while (more readback data)
 181                                 *addr++ = *fpga;
 182                         result = error ? STORE_FAIL_XXX : STORE_SUCCESS;
 183 #else
 184                         result = STORE_SUCCESS;
 185 #endif
 186
 187                         if (result == STORE_SUCCESS) {
 188                                 printf ("SUCCEEDED (%d bytes)\n",
 189                                         addr - save_addr);
 190                                 return 0;
 191                         } else
 192                                 printf ("FAILED (%d bytes)\n",
 193                                         addr - save_addr);
 194                         return 1;
 195                 }
 196                 break;
 197
 198         case 4:
 199                 if (strcmp (argv[1], "tftp") == 0) {
 200                         copy_filename (BootFile, argv[2], sizeof (BootFile));
 201                         load_addr = simple_strtoul (argv[3], NULL, 16);
 202                         NetBootFileXferSize = 0;
 203
 204                         if (NetLoop (TFTP) <= 0) {
 205                                 printf ("tftp transfer failed - aborting "
 206                                         "fgpa load\n");
 207                                 return 1;
 208                         }
 209
 210                         if (NetBootFileXferSize == 0) {
 211                                 printf ("can't determine file size - "
 212                                         "aborting fpga load\n");
 213                                 return 1;
 214                         }
 215
 216                         printf ("File transfer succeeded - "
 217                                 "beginning fpga load...");
 218
 219                         result = fpga_load (0, (uchar *) load_addr,
 220                                 NetBootFileXferSize);
 221
 222                         if (result == LOAD_SUCCESS) {
 223                                 printf ("SUCCEEDED\n");
 224                                 return 0;
 225                         } else if (result == LOAD_FAIL_NOCONF)
 226                                 printf ("FAILED (no CONF)\n");
 227                         else if (result == LOAD_FAIL_NOINIT)
 228                                 printf ("FAILED (no INIT)\n");
 229                         else
 230                                 printf ("FAILED (no DONE)\n");
 231                         return 1;
 232
 233                 }
 234                 /* fall through ... */
 235
 236         case 5:
 237                 if (strcmp (argv[1], "load") == 0) {
 238                         if (argc == 5) {
 239                                 if (strcmp (argv[2], "main") == 0)
 240                                         mezz = 0;
 241                                 else if (strcmp (argv[2], "mezz") == 0)
 242                                         mezz = 1;
 243                                 else {
 244                                         printf ("FPGA type must be either "
 245                                                 "`main' or `mezz'\n");
 246                                         return 1;
 247                                 }
 248                                 arg = 3;
 249                         } else {
 250                                 mezz = 0;
 251                                 arg = 2;
 252                         }
 253
 254                         addr = (uchar *) simple_strtoul (argv[arg++], NULL, 16);
 255                         size = (ulong) simple_strtoul (argv[arg], NULL, 16);
 256
 257                         result = fpga_load (mezz, addr, size);
 258
 259                         if (result == LOAD_SUCCESS) {
 260                                 printf ("SUCCEEDED\n");
 261                                 return 0;
 262                         } else if (result == LOAD_FAIL_NOCONF)
 263                                 printf ("FAILED (no CONF)\n");
 264                         else if (result == LOAD_FAIL_NOINIT)
 265                                 printf ("FAILED (no INIT)\n");
 266                         else
 267                                 printf ("FAILED (no DONE)\n");
 268                         return 1;
 269                 }
 270                 break;
 271
 272         default:
 273                 break;
 274         }
 275
 276         printf ("Usage:\n%s\n", cmdtp->usage);
 277         return 1;
 278 }
 279 cmd_tbl_t U_BOOT_CMD(fpga) = MK_CMD_ENTRY(
 280         "fpga", 6,      1,      do_fpga,
 281         "fpga    - FPGA sub-system\n",
 282         "load [type] addr size\n"
 283         "  - write the configuration data at memory address `addr',\n"
 284         "    size `size' bytes, into the FPGA of type `type' (either\n"
 285         "    `main' or `mezz', default `main'). e.g.\n"
 286         "        `fpga load 100000 7d8f'\n"
 287         "    loads the main FPGA with config data at address 100000\n"
 288         "    HEX, size 7d8f HEX (32143 DEC) bytes\n"
 289         "fpga tftp file addr\n"
 290         "  - transfers `file' from the tftp server into memory at\n"
 291         "    address `addr', then writes the entire file contents\n"
 292         "    into the main FPGA\n"
 293         "fpga store addr\n"
 294         "  - read configuration data from the main FPGA (the mezz\n"
 295         "    FPGA is write-only), into address `addr'. There must be\n"
 296         "    enough memory available at `addr' to hold all the config\n"
 297         "    data - the size of which is determined by VC:???\n"
 298         "fpga info\n"
 299         "  - print information about the Hymod FPGA, namely the\n"
 300         "    memory addresses at which the four FPGA local bus\n"
 301         "    address spaces appear in the physical address space\n"
 302 );
 303 /* ------------------------------------------------------------------------- */
 304 int
 305 do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 306 {
 307         uchar data[HYMOD_EEPROM_SIZE];
 308         uint addr = CFG_I2C_EEPROM_ADDR;
 309
 310         switch (argc) {
 311
 312         case 1:
 313                 addr |= HYMOD_EEOFF_MAIN;
 314                 break;
 315
 316         case 2:
 317                 if (strcmp (argv[1], "main") == 0) {
 318                         addr |= HYMOD_EEOFF_MAIN;
 319                         break;
 320                 }
 321                 if (strcmp (argv[1], "mezz") == 0) {
 322                         addr |= HYMOD_EEOFF_MEZZ;
 323                         break;
 324                 }
 325                 /* fall through ... */
 326
 327         default:
 328                 printf ("Usage:\n%s\n", cmdtp->usage);
 329                 return 1;
 330         }
 331
 332         memset (data, 0, HYMOD_EEPROM_SIZE);
 333
 334         eeprom_write (addr, 0, data, HYMOD_EEPROM_SIZE);
 335
 336         return 0;
 337 }
 338 cmd_tbl_t U_BOOT_CMD(eec) = MK_CMD_ENTRY(
 339         "eeclear",      1,      0,      do_eecl,
 340         "eeclear - Clear the eeprom on a Hymod board \n",
 341         "[type]\n"
 342         "  - write zeroes into the EEPROM on the board of type `type'\n"
 343         "    (`type' is either `main' or `mezz' - default `main')\n"
 344         "    Note: the EEPROM write enable jumper must be installed\n"
 345 );
 346
 347 /* ------------------------------------------------------------------------- */
 348
 349 int
 350 do_htest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 351 {
 352 #if 0
 353         int rc;
 354 #endif
 355 #ifdef CONFIG_ETHER_LOOPBACK_TEST
 356         extern void eth_loopback_test (void);
 357 #endif /* CONFIG_ETHER_LOOPBACK_TEST */
 358
 359         printf ("HYMOD tests - ensure loopbacks etc. are connected\n\n");
 360
 361 #if 0
 362         /* Load FPGA with test program */
 363
 364         printf ("Loading test FPGA program ...");
 365
 366         rc = fpga_load (0, test_bitfile, sizeof (test_bitfile));
 367
 368         switch (rc) {
 369
 370         case LOAD_SUCCESS:
 371                 printf (" SUCCEEDED\n");
 372                 break;
 373
 374         case LOAD_FAIL_NOCONF:
 375                 printf (" FAILED (no configuration space defined)\n");
 376                 return 1;
 377
 378         case LOAD_FAIL_NOINIT:
 379                 printf (" FAILED (timeout - no INIT signal seen)\n");
 380                 return 1;
 381
 382         case LOAD_FAIL_NODONE:
 383                 printf (" FAILED (timeout - no DONE signal seen)\n");
 384                 return 1;
 385
 386         default:
 387                 printf (" FAILED (unknown return code from fpga_load\n");
 388                 return 1;
 389         }
 390
 391         /* run Local Bus <=> Xilinx tests */
 392
 393         /* tell Xilinx to run ZBT Ram, High Speed serial and Mezzanine tests */
 394
 395         /* run SDRAM test */
 396 #endif
 397
 398 #ifdef CONFIG_ETHER_LOOPBACK_TEST
 399         /* run Ethernet test */
 400         eth_loopback_test ();
 401 #endif /* CONFIG_ETHER_LOOPBACK_TEST */
 402
 403         return 0;
 404 }
 405
 406 #endif  /* CFG_CMD_BSP */
 407
 408 /* ------------------------------------------------------------------------- */