board/hymod/hymod.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  *
   7  * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00
   8  */
   9
  10 #include <common.h>
  11 #include <mpc8260.h>
  12 #include <mpc8260_irq.h>
  13 #include <ioports.h>
  14 #include <i2c.h>
  15 #include <asm/iopin_8260.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 /* ------------------------------------------------------------------------- */
  20
  21 /* imports from eeprom.c */
  22 extern int hymod_eeprom_read (int, hymod_eeprom_t *);
  23 extern void hymod_eeprom_print (hymod_eeprom_t *);
  24
  25 /* imports from env.c */
  26 extern void hymod_check_env (void);
  27
  28 /* ------------------------------------------------------------------------- */
  29
  30 /*
  31  * I/O Port configuration table
  32  *
  33  * if conf is 1, then that port pin will be configured at boot time
  34  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  35  */
  36
  37 const iop_conf_t iop_conf_tab[4][32] = {
  38
  39         /* Port A configuration */
  40         {
  41                 /* cnf par sor dir odr dat */
  42                 {   1,  1,  1,  0,  0,  0   },  /* PA31: FCC1 MII COL */
  43                 {   1,  1,  1,  0,  0,  0   },  /* PA30: FCC1 MII CRS */
  44                 {   1,  1,  1,  1,  0,  0   },  /* PA29: FCC1 MII TX_ER */
  45                 {   1,  1,  1,  1,  0,  0   },  /* PA28: FCC1 MII TX_EN */
  46                 {   1,  1,  1,  0,  0,  0   },  /* PA27: FCC1 MII RX_DV */
  47                 {   1,  1,  1,  0,  0,  0   },  /* PA26: FCC1 MII RX_ER */
  48                 {   1,  0,  0,  1,  0,  0   },  /* PA25: FCC2 MII MDIO */
  49                 {   1,  0,  0,  1,  0,  0   },  /* PA24: FCC2 MII MDC */
  50                 {   1,  0,  0,  1,  0,  0   },  /* PA23: FCC3 MII MDIO */
  51                 {   1,  0,  0,  1,  0,  0   },  /* PA22: FCC3 MII MDC */
  52                 {   1,  1,  0,  1,  0,  0   },  /* PA21: FCC1 MII TxD[3] */
  53                 {   1,  1,  0,  1,  0,  0   },  /* PA20: FCC1 MII TxD[2] */
  54                 {   1,  1,  0,  1,  0,  0   },  /* PA19: FCC1 MII TxD[1] */
  55                 {   1,  1,  0,  1,  0,  0   },  /* PA18: FCC1 MII TxD[0] */
  56                 {   1,  1,  0,  0,  0,  0   },  /* PA17: FCC1 MII RxD[3] */
  57                 {   1,  1,  0,  0,  0,  0   },  /* PA16: FCC1 MII RxD[2] */
  58                 {   1,  1,  0,  0,  0,  0   },  /* PA15: FCC1 MII RxD[1] */
  59                 {   1,  1,  0,  0,  0,  0   },  /* PA14: FCC1 MII RxD[0] */
  60                 {   1,  0,  0,  1,  0,  0   },  /* PA13: FCC1 MII MDIO */
  61                 {   1,  0,  0,  1,  0,  0   },  /* PA12: FCC1 MII MDC */
  62                 {   1,  0,  0,  1,  0,  0   },  /* PA11: SEL_CD */
  63                 {   1,  0,  0,  0,  0,  0   },  /* PA10: FLASH STS1 */
  64                 {   1,  0,  0,  0,  0,  0   },  /* PA09: FLASH STS0 */
  65                 {   1,  0,  0,  0,  0,  0   },  /* PA08: FLASH ~PE */
  66                 {   1,  0,  0,  0,  0,  0   },  /* PA07: WATCH ~HRESET */
  67                 {   1,  0,  0,  0,  1,  0   },  /* PA06: VC DONE */
  68                 {   1,  0,  0,  1,  1,  0   },  /* PA05: VC INIT */
  69                 {   1,  0,  0,  1,  0,  0   },  /* PA04: VC ~PROG */
  70                 {   1,  0,  0,  1,  0,  0   },  /* PA03: VM ENABLE */
  71                 {   1,  0,  0,  0,  1,  0   },  /* PA02: VM DONE */
  72                 {   1,  0,  0,  1,  1,  0   },  /* PA01: VM INIT */
  73                 {   1,  0,  0,  1,  0,  0   }   /* PA00: VM ~PROG */
  74         },
  75
  76         /* Port B configuration */
  77         {
  78                 /* cnf par sor dir odr dat */
  79                 {   1,  1,  0,  1,  0,  0   },  /* PB31: FCC2 MII TX_ER */
  80                 {   1,  1,  0,  0,  0,  0   },  /* PB30: FCC2 MII RX_DV */
  81                 {   1,  1,  1,  1,  0,  0   },  /* PB29: FCC2 MII TX_EN */
  82                 {   1,  1,  0,  0,  0,  0   },  /* PB28: FCC2 MII RX_ER */
  83                 {   1,  1,  0,  0,  0,  0   },  /* PB27: FCC2 MII COL */
  84                 {   1,  1,  0,  0,  0,  0   },  /* PB26: FCC2 MII CRS */
  85                 {   1,  1,  0,  1,  0,  0   },  /* PB25: FCC2 MII TxD[3] */
  86                 {   1,  1,  0,  1,  0,  0   },  /* PB24: FCC2 MII TxD[2] */
  87                 {   1,  1,  0,  1,  0,  0   },  /* PB23: FCC2 MII TxD[1] */
  88                 {   1,  1,  0,  1,  0,  0   },  /* PB22: FCC2 MII TxD[0] */
  89                 {   1,  1,  0,  0,  0,  0   },  /* PB21: FCC2 MII RxD[0] */
  90                 {   1,  1,  0,  0,  0,  0   },  /* PB20: FCC2 MII RxD[1] */
  91                 {   1,  1,  0,  0,  0,  0   },  /* PB19: FCC2 MII RxD[2] */
  92                 {   1,  1,  0,  0,  0,  0   },  /* PB18: FCC2 MII RxD[3] */
  93                 {   1,  1,  0,  0,  0,  0   },  /* PB17: FCC3 MII RX_DV */
  94                 {   1,  1,  0,  0,  0,  0   },  /* PB16: FCC3 MII RX_ER */
  95                 {   1,  1,  0,  1,  0,  0   },  /* PB15: FCC3 MII TX_ER */
  96                 {   1,  1,  0,  1,  0,  0   },  /* PB14: FCC3 MII TX_EN */
  97                 {   1,  1,  0,  0,  0,  0   },  /* PB13: FCC3 MII COL */
  98                 {   1,  1,  0,  0,  0,  0   },  /* PB12: FCC3 MII CRS */
  99                 {   1,  1,  0,  0,  0,  0   },  /* PB11: FCC3 MII RxD[3] */
 100                 {   1,  1,  0,  0,  0,  0   },  /* PB10: FCC3 MII RxD[2] */
 101                 {   1,  1,  0,  0,  0,  0   },  /* PB09: FCC3 MII RxD[1] */
 102                 {   1,  1,  0,  0,  0,  0   },  /* PB08: FCC3 MII RxD[0] */
 103                 {   1,  1,  0,  1,  0,  0   },  /* PB07: FCC3 MII TxD[3] */
 104                 {   1,  1,  0,  1,  0,  0   },  /* PB06: FCC3 MII TxD[2] */
 105                 {   1,  1,  0,  1,  0,  0   },  /* PB05: FCC3 MII TxD[1] */
 106                 {   1,  1,  0,  1,  0,  0   },  /* PB04: FCC3 MII TxD[0] */
 107                 {   0,  0,  0,  0,  0,  0   },  /* PB03: pin doesn't exist */
 108                 {   0,  0,  0,  0,  0,  0   },  /* PB02: pin doesn't exist */
 109                 {   0,  0,  0,  0,  0,  0   },  /* PB01: pin doesn't exist */
 110                 {   0,  0,  0,  0,  0,  0   }   /* PB00: pin doesn't exist */
 111         },
 112
 113         /* Port C configuration */
 114         {
 115                 /* cnf par sor dir odr dat */
 116                 {   1,  0,  0,  0,  0,  0   },  /* PC31: MEZ ~IACK */
 117                 {   0,  0,  0,  0,  0,  0   },  /* PC30: ? */
 118                 {   1,  1,  0,  0,  0,  0   },  /* PC29: CLK SCCx */
 119                 {   1,  1,  0,  0,  0,  0   },  /* PC28: CLK4 */
 120                 {   1,  1,  0,  0,  0,  0   },  /* PC27: CLK SCCF */
 121                 {   1,  1,  0,  0,  0,  0   },  /* PC26: CLK 32K */
 122                 {   1,  1,  0,  0,  0,  0   },  /* PC25: BRG4/CLK7 */
 123                 {   0,  0,  0,  0,  0,  0   },  /* PC24: ? */
 124                 {   1,  1,  0,  0,  0,  0   },  /* PC23: CLK SCCx */
 125                 {   1,  1,  0,  0,  0,  0   },  /* PC22: FCC1 MII RX_CLK */
 126                 {   1,  1,  0,  0,  0,  0   },  /* PC21: FCC1 MII TX_CLK */
 127                 {   1,  1,  0,  0,  0,  0   },  /* PC20: CLK SCCF */
 128                 {   1,  1,  0,  0,  0,  0   },  /* PC19: FCC2 MII RX_CLK */
 129                 {   1,  1,  0,  0,  0,  0   },  /* PC18: FCC2 MII TX_CLK */
 130                 {   1,  1,  0,  0,  0,  0   },  /* PC17: FCC3 MII RX_CLK */
 131                 {   1,  1,  0,  0,  0,  0   },  /* PC16: FCC3 MII TX_CLK */
 132                 {   1,  0,  0,  0,  0,  0   },  /* PC15: SCC1 UART ~CTS */
 133                 {   1,  0,  0,  0,  0,  0   },  /* PC14: SCC1 UART ~CD */
 134                 {   1,  0,  0,  0,  0,  0   },  /* PC13: SCC2 UART ~CTS */
 135                 {   1,  0,  0,  0,  0,  0   },  /* PC12: SCC2 UART ~CD */
 136                 {   1,  0,  0,  1,  0,  0   },  /* PC11: SCC1 UART ~DTR */
 137                 {   1,  0,  0,  1,  0,  0   },  /* PC10: SCC1 UART ~DSR */
 138                 {   1,  0,  0,  1,  0,  0   },  /* PC09: SCC2 UART ~DTR */
 139                 {   1,  0,  0,  1,  0,  0   },  /* PC08: SCC2 UART ~DSR */
 140                 {   1,  0,  0,  0,  0,  0   },  /* PC07: TEMP ~ALERT */
 141                 {   1,  0,  0,  0,  0,  0   },  /* PC06: FCC3 INT */
 142                 {   1,  0,  0,  0,  0,  0   },  /* PC05: FCC2 INT */
 143                 {   1,  0,  0,  0,  0,  0   },  /* PC04: FCC1 INT */
 144                 {   0,  1,  1,  1,  0,  0   },  /* PC03: SDMA IDMA2 ~DACK */
 145                 {   0,  1,  1,  0,  0,  0   },  /* PC02: SDMA IDMA2 ~DONE */
 146                 {   0,  1,  0,  0,  0,  0   },  /* PC01: SDMA IDMA2 ~DREQ */
 147                 {   1,  1,  0,  1,  0,  0   }   /* PC00: BRG7 */
 148         },
 149
 150         /* Port D configuration */
 151         {
 152                 /* cnf par sor dir odr dat */
 153                 {   1,  1,  0,  0,  0,  0   },  /* PD31: SCC1 UART RxD */
 154                 {   1,  1,  1,  1,  0,  0   },  /* PD30: SCC1 UART TxD */
 155                 {   1,  0,  0,  1,  0,  0   },  /* PD29: SCC1 UART ~RTS */
 156                 {   1,  1,  0,  0,  0,  0   },  /* PD28: SCC2 UART RxD */
 157                 {   1,  1,  0,  1,  0,  0   },  /* PD27: SCC2 UART TxD */
 158                 {   1,  0,  0,  1,  0,  0   },  /* PD26: SCC2 UART ~RTS */
 159                 {   1,  0,  0,  0,  0,  0   },  /* PD25: SCC1 UART ~RI */
 160                 {   1,  0,  0,  0,  0,  0   },  /* PD24: SCC2 UART ~RI */
 161                 {   1,  0,  0,  1,  0,  0   },  /* PD23: CLKGEN PD */
 162                 {   1,  0,  0,  0,  0,  0   },  /* PD22: USER3 */
 163                 {   1,  0,  0,  0,  0,  0   },  /* PD21: USER2 */
 164                 {   1,  0,  0,  0,  0,  0   },  /* PD20: USER1 */
 165                 {   1,  1,  1,  0,  0,  0   },  /* PD19: SPI ~SEL */
 166                 {   1,  1,  1,  0,  0,  0   },  /* PD18: SPI CLK */
 167                 {   1,  1,  1,  0,  0,  0   },  /* PD17: SPI MOSI */
 168                 {   1,  1,  1,  0,  0,  0   },  /* PD16: SPI MISO */
 169                 {   1,  1,  1,  0,  1,  0   },  /* PD15: I2C SDA */
 170                 {   1,  1,  1,  0,  1,  0   },  /* PD14: I2C SCL */
 171                 {   1,  0,  0,  1,  0,  1   },  /* PD13: TEMP ~STDBY */
 172                 {   1,  0,  0,  1,  0,  1   },  /* PD12: FCC3 ~RESET */
 173                 {   1,  0,  0,  1,  0,  1   },  /* PD11: FCC2 ~RESET */
 174                 {   1,  0,  0,  1,  0,  1   },  /* PD10: FCC1 ~RESET */
 175                 {   1,  0,  0,  0,  0,  0   },  /* PD09: PD9 */
 176                 {   1,  0,  0,  0,  0,  0   },  /* PD08: PD8 */
 177                 {   1,  0,  0,  1,  0,  1   },  /* PD07: PD7 */
 178                 {   1,  0,  0,  1,  0,  1   },  /* PD06: PD6 */
 179                 {   1,  0,  0,  1,  0,  1   },  /* PD05: PD5 */
 180                 {   1,  0,  0,  1,  0,  1   },  /* PD04: PD4 */
 181                 {   0,  0,  0,  0,  0,  0   },  /* PD03: pin doesn't exist */
 182                 {   0,  0,  0,  0,  0,  0   },  /* PD02: pin doesn't exist */
 183                 {   0,  0,  0,  0,  0,  0   },  /* PD01: pin doesn't exist */
 184                 {   0,  0,  0,  0,  0,  0   }   /* PD00: pin doesn't exist */
 185         }
 186 };
 187
 188 /* ------------------------------------------------------------------------- */
 189
 190 /*
 191  * AMI FS6377 Clock Generator configuration table
 192  *
 193  * the "fs6377_regs[]" table entries correspond to FS6377 registers
 194  * 0 - 15 (total of 16 bytes).
 195  *
 196  * the data is written to the FS6377 via the i2c bus using address in
 197  * "fs6377_addr" (address is 7 bits - R/W bit not included).
 198  *
 199  * The fs6377 has four clock outputs: A, B, C and D.
 200  *
 201  * Outputs C and D can each provide two different clock outputs C1/D1 or
 202  * C2/D2 depending on the state of the SEL_CD input which is connected to
 203  * the MPC8260 I/O port pin PA11. PA11 output (SEL_CD input) low (or 0)
 204  * selects C1/D1 and PA11 output (SEL_CD input) high (or 1) selects C2/D2.
 205  *
 206  * PA11 defaults to output low (or 0) in the i/o port config table above.
 207  *
 208  * Output A provides a 100MHz for the High Speed Serial chips. Output B
 209  * provides a 3.6864MHz clock for more accurate asynchronous serial bit
 210  * rates. Output C is routed to the mezzanine connector but is currently
 211  * unused - both C1 and C2 are set to 16MHz. Output D is used by both the
 212  * alt-input and display mezzanine boards for their video chips. The
 213  * alt-input board requires a clock of 24.576MHz and this is available on
 214  * D1 (PA11=SEL_CD=0). The display board requires a clock of 27MHz and this
 215  * is available on D2 (PA11=SEL_CD=1).
 216  *
 217  * So the default is a clock suitable for the alt-input board. PA11 is toggled
 218  * later in misc_init_r(), if a display board is detected.
 219  */
 220
 221 uchar fs6377_addr = 0x5c;
 222
 223 uchar fs6377_regs[16] = {
 224          12,  75,  64,  25, 144, 128,  25, 192,
 225           0,  16, 135, 192, 224,  64,  64, 192
 226 };
 227
 228 /* ------------------------------------------------------------------------- */
 229
 230 /*
 231  * special board initialisation, after clocks and timebase have been
 232  * set up but before environment and serial are initialised.
 233  *
 234  * added so that very early initialisations can be done using the i2c
 235  * driver (which requires the clocks, to calculate the dividers, and
 236  * the timebase, for udelay())
 237  */
 238
 239 int
 240 board_postclk_init (void)
 241 {
 242         i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 243
 244         /*
 245          * Initialise the FS6377 clock chip
 246          *
 247          * the secondary address is the register number from where to
 248          * start the write - I want to write all the registers
 249          *
 250          * don't bother checking return status - we have no console yet
 251          * to print it on, nor any RAM to store it in - it will be obvious
 252          * if this doesn't work
 253          */
 254         (void) i2c_write (fs6377_addr, 0, 1, fs6377_regs,
 255                                         sizeof (fs6377_regs));
 256
 257         return (0);
 258 }
 259
 260 /* ------------------------------------------------------------------------- */
 261
 262 /*
 263  * Check Board Identity: Hardwired to HYMOD
 264  */
 265
 266 int
 267 checkboard (void)
 268 {
 269         puts ("Board: HYMOD\n");
 270         return (0);
 271 }
 272
 273 /* ------------------------------------------------------------------------- */
 274
 275 /*
 276  * miscellaneous (early - while running in flash) initialisations.
 277  */
 278
 279 #define _NOT_USED_      0xFFFFFFFF
 280
 281 uint upmb_table[] = {
 282         /* Read Single Beat (RSS) - offset 0x00 */
 283         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 284         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 285         /* Read Burst (RBS) - offset 0x08 */
 286         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 287         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 288         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 289         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 290         /* Write Single Beat (WSS) - offset 0x18 */
 291         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 292         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 293         /* Write Burst (WSS) - offset 0x20 */
 294         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 295         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 296         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 297         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 298         /* Refresh Timer (PTS) - offset 0x30 */
 299         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 300         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 301         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 302         /* Exception Condition (EXS) - offset 0x3c */
 303         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
 304 };
 305
 306 uint upmc_table[] = {
 307         /* Read Single Beat (RSS) - offset 0x00 */
 308         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 309         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 310         /* Read Burst (RBS) - offset 0x08 */
 311         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 312         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 313         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 314         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 315         /* Write Single Beat (WSS) - offset 0x18 */
 316         0xF0E00000, 0xF0A00000, 0x00A00000, 0x30A00000,
 317         0xF0F40007, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 318         /* Write Burst (WSS) - offset 0x20 */
 319         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 320         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 321         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 322         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 323         /* Refresh Timer (PTS) - offset 0x30 */
 324         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 325         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 326         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 327         /* Exception Condition (EXS) - offset 0x3c */
 328         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
 329 };
 330
 331 int
 332 misc_init_f (void)
 333 {
 334         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 335         volatile memctl8260_t *memctl = &immap->im_memctl;
 336
 337         printf ("UPMs:  ");
 338
 339         upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]);
 340         memctl->memc_mbmr = CONFIG_SYS_MBMR;
 341
 342         upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]);
 343         memctl->memc_mcmr = CONFIG_SYS_MCMR;
 344
 345         printf ("configured\n");
 346         return (0);
 347 }
 348
 349 /* ------------------------------------------------------------------------- */
 350
 351 phys_size_t
 352 initdram (int board_type)
 353 {
 354         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 355         volatile memctl8260_t *memctl = &immap->im_memctl;
 356         volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8);
 357         ulong psdmr = CONFIG_SYS_PSDMR;
 358         int i;
 359
 360         /*
 361          * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
 362          *
 363          * "At system reset, initialization software must set up the
 364          *  programmable parameters in the memory controller banks registers
 365          *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
 366          *  system software should execute the following initialization sequence
 367          *  for each SDRAM device.
 368          *
 369          *  1. Issue a PRECHARGE-ALL-BANKS command
 370          *  2. Issue eight CBR REFRESH commands
 371          *  3. Issue a MODE-SET command to initialize the mode register
 372          *
 373          *  The initial commands are executed by setting P/LSDMR[OP] and
 374          *  accessing the SDRAM with a single-byte transaction."
 375          *
 376          * The appropriate BRx/ORx registers have already been set when we
 377          * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 378          */
 379
 380         memctl->memc_psrt = CONFIG_SYS_PSRT;
 381         memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 382
 383         memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
 384         *ramaddr = c;
 385
 386         memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
 387         for (i = 0; i < 8; i++)
 388                 *ramaddr = c;
 389
 390         memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
 391         *ramaddr = c;
 392
 393         memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 394         *ramaddr = c;
 395
 396         return (CONFIG_SYS_SDRAM_SIZE << 20);
 397 }
 398
 399 /* ------------------------------------------------------------------------- */
 400 /* miscellaneous initialisations after relocation into ram (misc_init_r)     */
 401 /*                                                                           */
 402 /* loads the data in the main board and mezzanine board eeproms into         */
 403 /* the hymod configuration struct stored in the board information area.      */
 404 /*                                                                           */
 405 /* if the contents of either eeprom is invalid, prompts for a serial         */
 406 /* number (and an ethernet address if required) then fetches a file          */
 407 /* containing information to be stored in the eeprom from the tftp server    */
 408 /* (the file name is based on the serial number and a built-in path)         */
 409
 410 int
 411 last_stage_init (void)
 412 {
 413         hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
 414         int rc;
 415
 416 #ifdef CONFIG_BOOT_RETRY_TIME
 417         /*
 418          * we use the readline () function, but we also want
 419          * command timeout enabled
 420          */
 421         init_cmd_timeout ();
 422 #endif
 423
 424         memset ((void *) cp, 0, sizeof (*cp));
 425
 426         /* set up main board config info */
 427
 428         rc = hymod_eeprom_read (0, &cp->main.eeprom);
 429
 430         puts ("EEPROM:main...");
 431         if (rc < 0)
 432                 puts ("NOT PRESENT\n");
 433         else if (rc == 0)
 434                 puts ("INVALID\n");
 435         else {
 436                 cp->main.eeprom.valid = 1;
 437
 438                 printf ("OK (ver %u)\n", cp->main.eeprom.ver);
 439                 hymod_eeprom_print (&cp->main.eeprom);
 440
 441                 /*
 442                  * hard-wired assumption here: all hymod main boards will have
 443                  * one xilinx fpga, with the interrupt line connected to IRQ2
 444                  *
 445                  * One day, this might be based on the board type
 446                  */
 447
 448                 cp->main.xlx[0].mmap.prog.exists = 1;
 449                 cp->main.xlx[0].mmap.prog.size = FPGA_MAIN_CFG_SIZE;
 450                 cp->main.xlx[0].mmap.prog.base = FPGA_MAIN_CFG_BASE;
 451
 452                 cp->main.xlx[0].mmap.reg.exists = 1;
 453                 cp->main.xlx[0].mmap.reg.size = FPGA_MAIN_REG_SIZE;
 454                 cp->main.xlx[0].mmap.reg.base = FPGA_MAIN_REG_BASE;
 455
 456                 cp->main.xlx[0].mmap.port.exists = 1;
 457                 cp->main.xlx[0].mmap.port.size = FPGA_MAIN_PORT_SIZE;
 458                 cp->main.xlx[0].mmap.port.base = FPGA_MAIN_PORT_BASE;
 459
 460                 cp->main.xlx[0].iopins.prog_pin.port = FPGA_MAIN_PROG_PORT;
 461                 cp->main.xlx[0].iopins.prog_pin.pin = FPGA_MAIN_PROG_PIN;
 462                 cp->main.xlx[0].iopins.prog_pin.flag = 1;
 463                 cp->main.xlx[0].iopins.init_pin.port = FPGA_MAIN_INIT_PORT;
 464                 cp->main.xlx[0].iopins.init_pin.pin = FPGA_MAIN_INIT_PIN;
 465                 cp->main.xlx[0].iopins.init_pin.flag = 1;
 466                 cp->main.xlx[0].iopins.done_pin.port = FPGA_MAIN_DONE_PORT;
 467                 cp->main.xlx[0].iopins.done_pin.pin = FPGA_MAIN_DONE_PIN;
 468                 cp->main.xlx[0].iopins.done_pin.flag = 1;
 469 #ifdef FPGA_MAIN_ENABLE_PORT
 470                 cp->main.xlx[0].iopins.enable_pin.port = FPGA_MAIN_ENABLE_PORT;
 471                 cp->main.xlx[0].iopins.enable_pin.pin = FPGA_MAIN_ENABLE_PIN;
 472                 cp->main.xlx[0].iopins.enable_pin.flag = 1;
 473 #endif
 474
 475                 cp->main.xlx[0].irq = FPGA_MAIN_IRQ;
 476         }
 477
 478         /* set up mezzanine board config info */
 479
 480         rc = hymod_eeprom_read (1, &cp->mezz.eeprom);
 481
 482         puts ("EEPROM:mezz...");
 483         if (rc < 0)
 484                 puts ("NOT PRESENT\n");
 485         else if (rc == 0)
 486                 puts ("INVALID\n");
 487         else {
 488                 cp->main.eeprom.valid = 1;
 489
 490                 printf ("OK (ver %u)\n", cp->mezz.eeprom.ver);
 491                 hymod_eeprom_print (&cp->mezz.eeprom);
 492         }
 493
 494         cp->crc = crc32 (0, (unsigned char *)cp, offsetof (hymod_conf_t, crc));
 495
 496         hymod_check_env ();
 497
 498         return (0);
 499 }
 500
 501 #ifdef CONFIG_SHOW_ACTIVITY
 502 void board_show_activity (ulong timebase)
 503 {
 504 #ifdef CONFIG_SYS_HYMOD_DBLEDS
 505         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 506         volatile iop8260_t *iop = &immr->im_ioport;
 507         static int shift = 0;
 508
 509         if ((timestamp % CONFIG_SYS_HZ) == 0) {
 510                 if (++shift > 3)
 511                         shift = 0;
 512                 iop->iop_pdatd =
 513                                 (iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift));
 514         }
 515 #endif /* CONFIG_SYS_HYMOD_DBLEDS */
 516 }
 517
 518 void show_activity(int arg)
 519 {
 520 }
 521 #endif /* CONFIG_SHOW_ACTIVITY */