]> git.ipfire.org Git - people/ms/u-boot.git/blob - board/hymod/hymod.c
projects / people / ms / u-boot.git / blob
? search:


dea0a70a23a410aa68772a9226500080c64e5043
[people/ms/u-boot.git] / board / hymod / hymod.c
1 /*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00
24 */
25
26 #include <common.h>
27 #include <mpc8260.h>
28 #include <mpc8260_irq.h>
29 #include <ioports.h>
30 #include <i2c.h>
31 #include <asm/iopin_8260.h>
32
33 /* ------------------------------------------------------------------------- */
34
35 /* imports from eeprom.c */
36 extern int hymod_eeprom_read (int, hymod_eeprom_t *);
37 extern void hymod_eeprom_print (hymod_eeprom_t *);
38
39 /* imports from env.c */
40 extern void hymod_check_env (void);
41
42 /* ------------------------------------------------------------------------- */
43
44 /*
45 * I/O Port configuration table
46 *
47 * if conf is 1, then that port pin will be configured at boot time
48 * according to the five values podr/pdir/ppar/psor/pdat for that entry
49 */
50
51 const iop_conf_t iop_conf_tab[4][32] = {
52
53 /* Port A configuration */
54 {
55 /* cnf par sor dir odr dat */
56 { 1, 1, 1, 0, 0, 0 }, /* PA31: FCC1 MII COL */
57 { 1, 1, 1, 0, 0, 0 }, /* PA30: FCC1 MII CRS */
58 { 1, 1, 1, 1, 0, 0 }, /* PA29: FCC1 MII TX_ER */
59 { 1, 1, 1, 1, 0, 0 }, /* PA28: FCC1 MII TX_EN */
60 { 1, 1, 1, 0, 0, 0 }, /* PA27: FCC1 MII RX_DV */
61 { 1, 1, 1, 0, 0, 0 }, /* PA26: FCC1 MII RX_ER */
62 { 1, 0, 0, 1, 0, 0 }, /* PA25: FCC2 MII MDIO */
63 { 1, 0, 0, 1, 0, 0 }, /* PA24: FCC2 MII MDC */
64 { 1, 0, 0, 1, 0, 0 }, /* PA23: FCC3 MII MDIO */
65 { 1, 0, 0, 1, 0, 0 }, /* PA22: FCC3 MII MDC */
66 { 1, 1, 0, 1, 0, 0 }, /* PA21: FCC1 MII TxD[3] */
67 { 1, 1, 0, 1, 0, 0 }, /* PA20: FCC1 MII TxD[2] */
68 { 1, 1, 0, 1, 0, 0 }, /* PA19: FCC1 MII TxD[1] */
69 { 1, 1, 0, 1, 0, 0 }, /* PA18: FCC1 MII TxD[0] */
70 { 1, 1, 0, 0, 0, 0 }, /* PA17: FCC1 MII RxD[3] */
71 { 1, 1, 0, 0, 0, 0 }, /* PA16: FCC1 MII RxD[2] */
72 { 1, 1, 0, 0, 0, 0 }, /* PA15: FCC1 MII RxD[1] */
73 { 1, 1, 0, 0, 0, 0 }, /* PA14: FCC1 MII RxD[0] */
74 { 1, 0, 0, 1, 0, 0 }, /* PA13: FCC1 MII MDIO */
75 { 1, 0, 0, 1, 0, 0 }, /* PA12: FCC1 MII MDC */
76 { 1, 0, 0, 1, 0, 0 }, /* PA11: SEL_CD */
77 { 1, 0, 0, 0, 0, 0 }, /* PA10: FLASH STS1 */
78 { 1, 0, 0, 0, 0, 0 }, /* PA09: FLASH STS0 */
79 { 1, 0, 0, 0, 0, 0 }, /* PA08: FLASH ~PE */
80 { 1, 0, 0, 0, 0, 0 }, /* PA07: WATCH ~HRESET */
81 { 1, 0, 0, 0, 1, 0 }, /* PA06: VC DONE */
82 { 1, 0, 0, 1, 1, 0 }, /* PA05: VC INIT */
83 { 1, 0, 0, 1, 0, 0 }, /* PA04: VC ~PROG */
84 { 1, 0, 0, 1, 0, 0 }, /* PA03: VM ENABLE */
85 { 1, 0, 0, 0, 1, 0 }, /* PA02: VM DONE */
86 { 1, 0, 0, 1, 1, 0 }, /* PA01: VM INIT */
87 { 1, 0, 0, 1, 0, 0 } /* PA00: VM ~PROG */
88 },
89
90 /* Port B configuration */
91 {
92 /* cnf par sor dir odr dat */
93 { 1, 1, 0, 1, 0, 0 }, /* PB31: FCC2 MII TX_ER */
94 { 1, 1, 0, 0, 0, 0 }, /* PB30: FCC2 MII RX_DV */
95 { 1, 1, 1, 1, 0, 0 }, /* PB29: FCC2 MII TX_EN */
96 { 1, 1, 0, 0, 0, 0 }, /* PB28: FCC2 MII RX_ER */
97 { 1, 1, 0, 0, 0, 0 }, /* PB27: FCC2 MII COL */
98 { 1, 1, 0, 0, 0, 0 }, /* PB26: FCC2 MII CRS */
99 { 1, 1, 0, 1, 0, 0 }, /* PB25: FCC2 MII TxD[3] */
100 { 1, 1, 0, 1, 0, 0 }, /* PB24: FCC2 MII TxD[2] */
101 { 1, 1, 0, 1, 0, 0 }, /* PB23: FCC2 MII TxD[1] */
102 { 1, 1, 0, 1, 0, 0 }, /* PB22: FCC2 MII TxD[0] */
103 { 1, 1, 0, 0, 0, 0 }, /* PB21: FCC2 MII RxD[0] */
104 { 1, 1, 0, 0, 0, 0 }, /* PB20: FCC2 MII RxD[1] */
105 { 1, 1, 0, 0, 0, 0 }, /* PB19: FCC2 MII RxD[2] */
106 { 1, 1, 0, 0, 0, 0 }, /* PB18: FCC2 MII RxD[3] */
107 { 1, 1, 0, 0, 0, 0 }, /* PB17: FCC3 MII RX_DV */
108 { 1, 1, 0, 0, 0, 0 }, /* PB16: FCC3 MII RX_ER */
109 { 1, 1, 0, 1, 0, 0 }, /* PB15: FCC3 MII TX_ER */
110 { 1, 1, 0, 1, 0, 0 }, /* PB14: FCC3 MII TX_EN */
111 { 1, 1, 0, 0, 0, 0 }, /* PB13: FCC3 MII COL */
112 { 1, 1, 0, 0, 0, 0 }, /* PB12: FCC3 MII CRS */
113 { 1, 1, 0, 0, 0, 0 }, /* PB11: FCC3 MII RxD[3] */
114 { 1, 1, 0, 0, 0, 0 }, /* PB10: FCC3 MII RxD[2] */
115 { 1, 1, 0, 0, 0, 0 }, /* PB09: FCC3 MII RxD[1] */
116 { 1, 1, 0, 0, 0, 0 }, /* PB08: FCC3 MII RxD[0] */
117 { 1, 1, 0, 1, 0, 0 }, /* PB07: FCC3 MII TxD[3] */
118 { 1, 1, 0, 1, 0, 0 }, /* PB06: FCC3 MII TxD[2] */
119 { 1, 1, 0, 1, 0, 0 }, /* PB05: FCC3 MII TxD[1] */
120 { 1, 1, 0, 1, 0, 0 }, /* PB04: FCC3 MII TxD[0] */
121 { 0, 0, 0, 0, 0, 0 }, /* PB03: pin doesn't exist */
122 { 0, 0, 0, 0, 0, 0 }, /* PB02: pin doesn't exist */
123 { 0, 0, 0, 0, 0, 0 }, /* PB01: pin doesn't exist */
124 { 0, 0, 0, 0, 0, 0 } /* PB00: pin doesn't exist */
125 },
126
127 /* Port C configuration */
128 {
129 /* cnf par sor dir odr dat */
130 { 1, 0, 0, 0, 0, 0 }, /* PC31: MEZ ~IACK */
131 { 0, 0, 0, 0, 0, 0 }, /* PC30: ? */
132 { 1, 1, 0, 0, 0, 0 }, /* PC29: CLK SCCx */
133 { 1, 1, 0, 0, 0, 0 }, /* PC28: CLK4 */
134 { 1, 1, 0, 0, 0, 0 }, /* PC27: CLK SCCF */
135 { 1, 1, 0, 0, 0, 0 }, /* PC26: CLK 32K */
136 { 1, 1, 0, 0, 0, 0 }, /* PC25: BRG4/CLK7 */
137 { 0, 0, 0, 0, 0, 0 }, /* PC24: ? */
138 { 1, 1, 0, 0, 0, 0 }, /* PC23: CLK SCCx */
139 { 1, 1, 0, 0, 0, 0 }, /* PC22: FCC1 MII RX_CLK */
140 { 1, 1, 0, 0, 0, 0 }, /* PC21: FCC1 MII TX_CLK */
141 { 1, 1, 0, 0, 0, 0 }, /* PC20: CLK SCCF */
142 { 1, 1, 0, 0, 0, 0 }, /* PC19: FCC2 MII RX_CLK */
143 { 1, 1, 0, 0, 0, 0 }, /* PC18: FCC2 MII TX_CLK */
144 { 1, 1, 0, 0, 0, 0 }, /* PC17: FCC3 MII RX_CLK */
145 { 1, 1, 0, 0, 0, 0 }, /* PC16: FCC3 MII TX_CLK */
146 { 1, 0, 0, 0, 0, 0 }, /* PC15: SCC1 UART ~CTS */
147 { 1, 0, 0, 0, 0, 0 }, /* PC14: SCC1 UART ~CD */
148 { 1, 0, 0, 0, 0, 0 }, /* PC13: SCC2 UART ~CTS */
149 { 1, 0, 0, 0, 0, 0 }, /* PC12: SCC2 UART ~CD */
150 { 1, 0, 0, 1, 0, 0 }, /* PC11: SCC1 UART ~DTR */
151 { 1, 0, 0, 1, 0, 0 }, /* PC10: SCC1 UART ~DSR */
152 { 1, 0, 0, 1, 0, 0 }, /* PC09: SCC2 UART ~DTR */
153 { 1, 0, 0, 1, 0, 0 }, /* PC08: SCC2 UART ~DSR */
154 { 1, 0, 0, 0, 0, 0 }, /* PC07: TEMP ~ALERT */
155 { 1, 0, 0, 0, 0, 0 }, /* PC06: FCC3 INT */
156 { 1, 0, 0, 0, 0, 0 }, /* PC05: FCC2 INT */
157 { 1, 0, 0, 0, 0, 0 }, /* PC04: FCC1 INT */
158 { 0, 1, 1, 1, 0, 0 }, /* PC03: SDMA IDMA2 ~DACK */
159 { 0, 1, 1, 0, 0, 0 }, /* PC02: SDMA IDMA2 ~DONE */
160 { 0, 1, 0, 0, 0, 0 }, /* PC01: SDMA IDMA2 ~DREQ */
161 { 1, 1, 0, 1, 0, 0 } /* PC00: BRG7 */
162 },
163
164 /* Port D configuration */
165 {
166 /* cnf par sor dir odr dat */
167 { 1, 1, 0, 0, 0, 0 }, /* PD31: SCC1 UART RxD */
168 { 1, 1, 1, 1, 0, 0 }, /* PD30: SCC1 UART TxD */
169 { 1, 0, 0, 1, 0, 0 }, /* PD29: SCC1 UART ~RTS */
170 { 1, 1, 0, 0, 0, 0 }, /* PD28: SCC2 UART RxD */
171 { 1, 1, 0, 1, 0, 0 }, /* PD27: SCC2 UART TxD */
172 { 1, 0, 0, 1, 0, 0 }, /* PD26: SCC2 UART ~RTS */
173 { 1, 0, 0, 0, 0, 0 }, /* PD25: SCC1 UART ~RI */
174 { 1, 0, 0, 0, 0, 0 }, /* PD24: SCC2 UART ~RI */
175 { 1, 0, 0, 1, 0, 0 }, /* PD23: CLKGEN PD */
176 { 1, 0, 0, 0, 0, 0 }, /* PD22: USER3 */
177 { 1, 0, 0, 0, 0, 0 }, /* PD21: USER2 */
178 { 1, 0, 0, 0, 0, 0 }, /* PD20: USER1 */
179 { 1, 1, 1, 0, 0, 0 }, /* PD19: SPI ~SEL */
180 { 1, 1, 1, 0, 0, 0 }, /* PD18: SPI CLK */
181 { 1, 1, 1, 0, 0, 0 }, /* PD17: SPI MOSI */
182 { 1, 1, 1, 0, 0, 0 }, /* PD16: SPI MISO */
183 { 1, 1, 1, 0, 1, 0 }, /* PD15: I2C SDA */
184 { 1, 1, 1, 0, 1, 0 }, /* PD14: I2C SCL */
185 { 1, 0, 0, 1, 0, 1 }, /* PD13: TEMP ~STDBY */
186 { 1, 0, 0, 1, 0, 1 }, /* PD12: FCC3 ~RESET */
187 { 1, 0, 0, 1, 0, 1 }, /* PD11: FCC2 ~RESET */
188 { 1, 0, 0, 1, 0, 1 }, /* PD10: FCC1 ~RESET */
189 { 1, 0, 0, 0, 0, 0 }, /* PD09: PD9 */
190 { 1, 0, 0, 0, 0, 0 }, /* PD08: PD8 */
191 { 1, 0, 0, 1, 0, 1 }, /* PD07: PD7 */
192 { 1, 0, 0, 1, 0, 1 }, /* PD06: PD6 */
193 { 1, 0, 0, 1, 0, 1 }, /* PD05: PD5 */
194 { 1, 0, 0, 1, 0, 1 }, /* PD04: PD4 */
195 { 0, 0, 0, 0, 0, 0 }, /* PD03: pin doesn't exist */
196 { 0, 0, 0, 0, 0, 0 }, /* PD02: pin doesn't exist */
197 { 0, 0, 0, 0, 0, 0 }, /* PD01: pin doesn't exist */
198 { 0, 0, 0, 0, 0, 0 } /* PD00: pin doesn't exist */
199 }
200 };
201
202 /* ------------------------------------------------------------------------- */
203
204 /*
205 * AMI FS6377 Clock Generator configuration table
206 *
207 * the "fs6377_regs[]" table entries correspond to FS6377 registers
208 * 0 - 15 (total of 16 bytes).
209 *
210 * the data is written to the FS6377 via the i2c bus using address in
211 * "fs6377_addr" (address is 7 bits - R/W bit not included).
212 *
213 * The fs6377 has four clock outputs: A, B, C and D.
214 *
215 * Outputs C and D can each provide two different clock outputs C1/D1 or
216 * C2/D2 depending on the state of the SEL_CD input which is connected to
217 * the MPC8260 I/O port pin PA11. PA11 output (SEL_CD input) low (or 0)
218 * selects C1/D1 and PA11 output (SEL_CD input) high (or 1) selects C2/D2.
219 *
220 * PA11 defaults to output low (or 0) in the i/o port config table above.
221 *
222 * Output A provides a 100MHz for the High Speed Serial chips. Output B
223 * provides a 3.6864MHz clock for more accurate asynchronous serial bit
224 * rates. Output C is routed to the mezzanine connector but is currently
225 * unused - both C1 and C2 are set to 16MHz. Output D is used by both the
226 * alt-input and display mezzanine boards for their video chips. The
227 * alt-input board requires a clock of 24.576MHz and this is available on
228 * D1 (PA11=SEL_CD=0). The display board requires a clock of 27MHz and this
229 * is available on D2 (PA11=SEL_CD=1).
230 *
231 * So the default is a clock suitable for the alt-input board. PA11 is toggled
232 * later in misc_init_r(), if a display board is detected.
233 */
234
235 uchar fs6377_addr = 0x5c;
236
237 uchar fs6377_regs[16] = {
238 12, 75, 64, 25, 144, 128, 25, 192,
239 0, 16, 135, 192, 224, 64, 64, 192
240 };
241
242 /* ------------------------------------------------------------------------- */
243
244 /*
245 * special board initialisation, after clocks and timebase have been
246 * set up but before environment and serial are initialised.
247 *
248 * added so that very early initialisations can be done using the i2c
249 * driver (which requires the clocks, to calculate the dividers, and
250 * the timebase, for udelay())
251 */
252
253 int
254 board_postclk_init (void)
255 {
256 i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
257
258 /*
259 * Initialise the FS6377 clock chip
260 *
261 * the secondary address is the register number from where to
262 * start the write - I want to write all the registers
263 *
264 * don't bother checking return status - we have no console yet
265 * to print it on, nor any RAM to store it in - it will be obvious
266 * if this doesn't work
267 */
268 (void) i2c_write (fs6377_addr, 0, 1, fs6377_regs,
269 sizeof (fs6377_regs));
270
271 return (0);
272 }
273
274 /* ------------------------------------------------------------------------- */
275
276 /*
277 * Check Board Identity: Hardwired to HYMOD
278 */
279
280 int
281 checkboard (void)
282 {
283 puts ("Board: HYMOD\n");
284 return (0);
285 }
286
287 /* ------------------------------------------------------------------------- */
288
289 /*
290 * miscellaneous (early - while running in flash) initialisations.
291 */
292
293 #define _NOT_USED_ 0xFFFFFFFF
294
295 uint upmb_table[] = {
296 /* Read Single Beat (RSS) - offset 0x00 */
297 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
298 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
299 /* Read Burst (RBS) - offset 0x08 */
300 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
301 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
302 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
303 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
304 /* Write Single Beat (WSS) - offset 0x18 */
305 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
306 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
307 /* Write Burst (WSS) - offset 0x20 */
308 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
309 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
310 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
311 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
312 /* Refresh Timer (PTS) - offset 0x30 */
313 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
314 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
315 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
316 /* Exception Condition (EXS) - offset 0x3c */
317 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
318 };
319
320 uint upmc_table[] = {
321 /* Read Single Beat (RSS) - offset 0x00 */
322 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
323 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
324 /* Read Burst (RBS) - offset 0x08 */
325 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
326 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
327 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
328 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
329 /* Write Single Beat (WSS) - offset 0x18 */
330 0xF0E00000, 0xF0A00000, 0x00A00000, 0x30A00000,
331 0xF0F40007, _NOT_USED_, _NOT_USED_, _NOT_USED_,
332 /* Write Burst (WSS) - offset 0x20 */
333 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
334 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
335 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
336 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
337 /* Refresh Timer (PTS) - offset 0x30 */
338 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
339 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
340 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
341 /* Exception Condition (EXS) - offset 0x3c */
342 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
343 };
344
345 int
346 misc_init_f (void)
347 {
348 volatile immap_t *immap = (immap_t *) CFG_IMMR;
349 volatile memctl8260_t *memctl = &immap->im_memctl;
350
351 printf ("UPMs: ");
352
353 upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]);
354 memctl->memc_mbmr = CFG_MBMR;
355
356 upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]);
357 memctl->memc_mcmr = CFG_MCMR;
358
359 printf ("configured\n");
360 return (0);
361 }
362
363 /* ------------------------------------------------------------------------- */
364
365 long
366 initdram (int board_type)
367 {
368 volatile immap_t *immap = (immap_t *) CFG_IMMR;
369 volatile memctl8260_t *memctl = &immap->im_memctl;
370 volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8);
371 ulong psdmr = CFG_PSDMR;
372 int i;
373
374 /*
375 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
376 *
377 * "At system reset, initialization software must set up the
378 * programmable parameters in the memory controller banks registers
379 * (ORx, BRx, P/LSDMR). After all memory parameters are conÞgured,
380 * system software should execute the following initialization sequence
381 * for each SDRAM device.
382 *
383 * 1. Issue a PRECHARGE-ALL-BANKS command
384 * 2. Issue eight CBR REFRESH commands
385 * 3. Issue a MODE-SET command to initialize the mode register
386 *
387 * The initial commands are executed by setting P/LSDMR[OP] and
388 * accessing the SDRAM with a single-byte transaction."
389 *
390 * The appropriate BRx/ORx registers have already been set when we
391 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
392 */
393
394 memctl->memc_psrt = CFG_PSRT;
395 memctl->memc_mptpr = CFG_MPTPR;
396
397 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
398 *ramaddr = c;
399
400 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
401 for (i = 0; i < 8; i++)
402 *ramaddr = c;
403
404 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
405 *ramaddr = c;
406
407 memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
408 *ramaddr = c;
409
410 return (CFG_SDRAM_SIZE << 20);
411 }
412
413 /* ------------------------------------------------------------------------- */
414 /* miscellaneous initialisations after relocation into ram (misc_init_r) */
415 /* */
416 /* loads the data in the main board and mezzanine board eeproms into */
417 /* the hymod configuration struct stored in the board information area. */
418 /* */
419 /* if the contents of either eeprom is invalid, prompts for a serial */
420 /* number (and an ethernet address if required) then fetches a file */
421 /* containing information to be stored in the eeprom from the tftp server */
422 /* (the file name is based on the serial number and a built-in path) */
423
424 int
425 last_stage_init (void)
426 {
427 DECLARE_GLOBAL_DATA_PTR;
428
429 hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
430 int rc;
431
432 #ifdef CONFIG_BOOT_RETRY_TIME
433 /*
434 * we use the readline () function, but we also want
435 * command timeout enabled
436 */
437 init_cmd_timeout ();
438 #endif
439
440 memset ((void *) cp, 0, sizeof (*cp));
441
442 /* set up main board config info */
443
444 rc = hymod_eeprom_read (0, &cp->main.eeprom);
445
446 puts ("EEPROM:main...");
447 if (rc < 0)
448 puts ("NOT PRESENT\n");
449 else if (rc == 0)
450 puts ("INVALID\n");
451 else {
452 cp->main.eeprom.valid = 1;
453
454 printf ("OK (ver %u)\n", cp->main.eeprom.ver);
455 hymod_eeprom_print (&cp->main.eeprom);
456
457 /*
458 * hard-wired assumption here: all hymod main boards will have
459 * one xilinx fpga, with the interrupt line connected to IRQ2
460 *
461 * One day, this might be based on the board type
462 */
463
464 cp->main.xlx[0].mmap.prog.exists = 1;
465 cp->main.xlx[0].mmap.prog.size = FPGA_MAIN_CFG_SIZE;
466 cp->main.xlx[0].mmap.prog.base = FPGA_MAIN_CFG_BASE;
467
468 cp->main.xlx[0].mmap.reg.exists = 1;
469 cp->main.xlx[0].mmap.reg.size = FPGA_MAIN_REG_SIZE;
470 cp->main.xlx[0].mmap.reg.base = FPGA_MAIN_REG_BASE;
471
472 cp->main.xlx[0].mmap.port.exists = 1;
473 cp->main.xlx[0].mmap.port.size = FPGA_MAIN_PORT_SIZE;
474 cp->main.xlx[0].mmap.port.base = FPGA_MAIN_PORT_BASE;
475
476 cp->main.xlx[0].iopins.prog_pin.port = FPGA_MAIN_PROG_PORT;
477 cp->main.xlx[0].iopins.prog_pin.pin = FPGA_MAIN_PROG_PIN;
478 cp->main.xlx[0].iopins.prog_pin.flag = 1;
479 cp->main.xlx[0].iopins.init_pin.port = FPGA_MAIN_INIT_PORT;
480 cp->main.xlx[0].iopins.init_pin.pin = FPGA_MAIN_INIT_PIN;
481 cp->main.xlx[0].iopins.init_pin.flag = 1;
482 cp->main.xlx[0].iopins.done_pin.port = FPGA_MAIN_DONE_PORT;
483 cp->main.xlx[0].iopins.done_pin.pin = FPGA_MAIN_DONE_PIN;
484 cp->main.xlx[0].iopins.done_pin.flag = 1;
485 #ifdef FPGA_MAIN_ENABLE_PORT
486 cp->main.xlx[0].iopins.enable_pin.port = FPGA_MAIN_ENABLE_PORT;
487 cp->main.xlx[0].iopins.enable_pin.pin = FPGA_MAIN_ENABLE_PIN;
488 cp->main.xlx[0].iopins.enable_pin.flag = 1;
489 #endif
490
491 cp->main.xlx[0].irq = FPGA_MAIN_IRQ;
492 }
493
494 /* set up mezzanine board config info */
495
496 rc = hymod_eeprom_read (1, &cp->mezz.eeprom);
497
498 puts ("EEPROM:mezz...");
499 if (rc < 0)
500 puts ("NOT PRESENT\n");
501 else if (rc == 0)
502 puts ("INVALID\n");
503 else {
504 cp->main.eeprom.valid = 1;
505
506 printf ("OK (ver %u)\n", cp->mezz.eeprom.ver);
507 hymod_eeprom_print (&cp->mezz.eeprom);
508 }
509
510 cp->crc = crc32 (0, (unsigned char *)cp, offsetof (hymod_conf_t, crc));
511
512 hymod_check_env ();
513
514 return (0);
515 }
516
517 #ifdef CONFIG_SHOW_ACTIVITY
518 void board_show_activity (ulong timebase)
519 {
520 #ifdef CFG_HYMOD_DBLEDS
521 volatile immap_t *immr = (immap_t *) CFG_IMMR;
522 volatile iop8260_t *iop = &immr->im_ioport;
523 static int shift = 0;
524
525 if ((timestamp % CFG_HZ) == 0) {
526 if (++shift > 3)
527 shift = 0;
528 iop->iop_pdatd =
529 (iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift));
530 }
531 #endif /* CFG_HYMOD_DBLEDS */
532 }
533
534 void show_activity(int arg)
535 {
536 }
537 #endif /* CONFIG_SHOW_ACTIVITY */
"Das U-Boot" Source Tree