board/icu862/icu862.c

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <config.h>
  10 #include <mpc8xx.h>
  11
  12 /*
  13  *  Memory Controller Using
  14  *
  15  *  CS0 - Flash memory            (0x40000000)
  16  *  CS1 - SDRAM                   (0x00000000}
  17  *  CS2 - S/UNI Ultra ATM155
  18  *  CS3 - IDT 77106 ATM25
  19  *  CS4 - DSP HPI
  20  *  CS5 - E1/T1 Interface device
  21  *  CS6 - PCMCIA device
  22  *  CS7 - PCMCIA device
  23  */
  24
  25 /* ------------------------------------------------------------------------- */
  26
  27 #define _not_used_      0xffffffff
  28
  29 const uint sdram_table[] = {
  30         /* single read. (offset 0 in upm RAM) */
  31         0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
  32         0x1ff77c47,
  33
  34         /* MRS initialization (offset 5) */
  35
  36         0x1ff77c34, 0xefeabc34, 0x1fb57c35,
  37
  38         /* burst read. (offset 8 in upm RAM) */
  39         0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
  40         0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
  41         _not_used_, _not_used_, _not_used_, _not_used_,
  42         _not_used_, _not_used_, _not_used_, _not_used_,
  43
  44         /* single write. (offset 18 in upm RAM) */
  45         0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
  46         _not_used_, _not_used_, _not_used_, _not_used_,
  47
  48         /* burst write. (offset 20 in upm RAM) */
  49         0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
  50         0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
  51         _not_used_, _not_used_, _not_used_, _not_used_,
  52         _not_used_, _not_used_, _not_used_, _not_used_,
  53
  54         /* refresh. (offset 30 in upm RAM) */
  55         0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  56         0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
  57         _not_used_, _not_used_, _not_used_, _not_used_,
  58
  59         /* exception. (offset 3c in upm RAM) */
  60         0x7ffffc07, _not_used_, _not_used_, _not_used_
  61 };
  62
  63 /* ------------------------------------------------------------------------- */
  64
  65 /*
  66  * Check Board Identity:
  67  */
  68
  69 int checkboard (void)
  70 {
  71         puts ("Board: ICU862 Board\n");
  72         return 0;
  73 }
  74
  75 /* ------------------------------------------------------------------------- */
  76
  77 static long int dram_size (long int, long int *, long int);
  78
  79 /* ------------------------------------------------------------------------- */
  80
  81 phys_size_t initdram (int board_type)
  82 {
  83         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  84         volatile memctl8xx_t *memctl = &immap->im_memctl;
  85         long int size8, size9;
  86         long int size_b0 = 0;
  87         unsigned long reg;
  88
  89         upmconfig (UPMA, (uint *) sdram_table,
  90                            sizeof (sdram_table) / sizeof (uint));
  91
  92         /*
  93          * Preliminary prescaler for refresh (depends on number of
  94          * banks): This value is selected for four cycles every 62.4 us
  95          * with two SDRAM banks or four cycles every 31.2 us with one
  96          * bank. It will be adjusted after memory sizing.
  97          */
  98         memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
  99
 100         memctl->memc_mar = 0x00000088;
 101
 102         /*
 103          * Map controller bank 1 to the SDRAM bank at
 104          * preliminary address - these have to be modified after the
 105          * SDRAM size has been determined.
 106          */
 107         memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
 108         memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 109
 110         memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));      /* no refresh yet */
 111
 112         udelay (200);
 113
 114         /* perform SDRAM initializsation sequence */
 115
 116         memctl->memc_mcr = 0x80002105;  /* SDRAM bank 0 */
 117         udelay (200);
 118         memctl->memc_mcr = 0x80002230;  /* SDRAM bank 0 - execute twice */
 119         udelay (200);
 120
 121         memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
 122
 123         udelay (1000);
 124
 125         /*
 126          * Check Bank 0 Memory Size for re-configuration
 127          *
 128          * try 8 column mode
 129          */
 130         size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE1_PRELIM,
 131                                            SDRAM_MAX_SIZE);
 132
 133         udelay (1000);
 134
 135         /*
 136          * try 9 column mode
 137          */
 138         size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE1_PRELIM,
 139                                            SDRAM_MAX_SIZE);
 140
 141         if (size8 < size9) {            /* leave configuration at 9 columns */
 142                 size_b0 = size9;
 143 /*      debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);  */
 144         } else {                                        /* back to 8 columns            */
 145                 size_b0 = size8;
 146                 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 147                 udelay (500);
 148 /*      debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);  */
 149         }
 150
 151         udelay (1000);
 152
 153         /*
 154          * Adjust refresh rate depending on SDRAM type, both banks
 155          * For types > 128 MBit leave it at the current (fast) rate
 156          */
 157         if ((size_b0 < 0x02000000)) {
 158                 /* reduce to 15.6 us (62.4 us / quad) */
 159                 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 160                 udelay (1000);
 161         }
 162
 163         /*
 164          * Final mapping
 165          */
 166
 167         memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 168         memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 169
 170         /* adjust refresh rate depending on SDRAM type, one bank */
 171         reg = memctl->memc_mptpr;
 172         reg >>= 1;                                      /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 173         memctl->memc_mptpr = reg;
 174
 175         udelay (10000);
 176
 177         return (size_b0);
 178 }
 179
 180 /* ------------------------------------------------------------------------- */
 181
 182 /*
 183  * Check memory range for valid RAM. A simple memory test determines
 184  * the actually available RAM size between addresses `base' and
 185  * `base + maxsize'. Some (not all) hardware errors are detected:
 186  * - short between address lines
 187  * - short between data lines
 188  */
 189
 190 static long int dram_size (long int mamr_value, long int *base,
 191                                                    long int maxsize)
 192 {
 193         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 194         volatile memctl8xx_t *memctl = &immap->im_memctl;
 195
 196         memctl->memc_mamr = mamr_value;
 197
 198         return (get_ram_size(base, maxsize));
 199 }