board/ifm/ac14xx/ac14xx.c

   1 /*
   2  * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
   3  * (C) Copyright 2009 Dave Srl www.dave.eu
   4  * (C) Copyright 2010 ifm ecomatic GmbH
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/bitops.h>
  11 #include <command.h>
  12 #include <asm/io.h>
  13 #include <asm/processor.h>
  14 #include <asm/mpc512x.h>
  15 #include <fdt_support.h>
  16 #ifdef CONFIG_MISC_INIT_R
  17 #include <i2c.h>
  18 #endif
  19
  20 static int eeprom_diag;
  21 static int mac_diag;
  22 static int gpio_diag;
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 static void gpio_configure(void)
  27 {
  28         immap_t *im;
  29         gpio512x_t *gpioregs;
  30
  31         im = (immap_t *) CONFIG_SYS_IMMR;
  32         gpioregs = &im->gpio;
  33         out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
  34         out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */
  35
  36         /*
  37          * out_be32(&gpioregs->gpdir, 0xC2293020);
  38          * workaround for a hardware effect: configure direction in pieces,
  39          * setting all outputs at once drops the reset line too low and
  40          * makes us lose the MII connection (breaks ethernet for us)
  41          */
  42         out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
  43         setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
  44         udelay(10);
  45         setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
  46         udelay(10);
  47         setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
  48         udelay(10);
  49         setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */
  50
  51         /* to turn from red to yellow when U-Boot runs */
  52         setbits_be32(&gpioregs->gpdat, 0x00002020);
  53         out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
  54         out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
  55         out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
  56         out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
  57 }
  58
  59 /* the physical location of the pins */
  60 #define GPIOKEY_ROW_BITMASK     0x40000000
  61 #define GPIOKEY_ROW_UPPER       0
  62 #define GPIOKEY_ROW_LOWER       1
  63
  64 #define GPIOKEY_COL0_BITMASK    0x20000000
  65 #define GPIOKEY_COL1_BITMASK    0x10000000
  66 #define GPIOKEY_COL2_BITMASK    0x08000000
  67
  68 /* the logical presentation of pressed keys */
  69 #define GPIOKEY_BIT_FNLEFT      (1 << 5)
  70 #define GPIOKEY_BIT_FNRIGHT     (1 << 4)
  71 #define GPIOKEY_BIT_DIRUP       (1 << 3)
  72 #define GPIOKEY_BIT_DIRLEFT     (1 << 2)
  73 #define GPIOKEY_BIT_DIRRIGHT    (1 << 1)
  74 #define GPIOKEY_BIT_DIRDOWN     (1 << 0)
  75
  76 /* the hotkey combination which starts recovery */
  77 #define GPIOKEY_BITS_RECOVERY   (GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \
  78                                  GPIOKEY_BIT_DIRDOWN)
  79
  80 static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
  81 {
  82
  83         if (row)
  84                 setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
  85         else
  86                 clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
  87         udelay(10);
  88 }
  89
  90 static u32 gpio_querykbd(void)
  91 {
  92         immap_t *im;
  93         gpio512x_t *gpioregs;
  94         u32 keybits;
  95         u32 input;
  96
  97         im = (immap_t *)CONFIG_SYS_IMMR;
  98         gpioregs = &im->gpio;
  99         keybits = 0;
 100
 101         /* query upper row */
 102         gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
 103         input = in_be32(&gpioregs->gpdat);
 104         if ((input & GPIOKEY_COL0_BITMASK) == 0)
 105                 keybits |= GPIOKEY_BIT_FNLEFT;
 106         if ((input & GPIOKEY_COL1_BITMASK) == 0)
 107                 keybits |= GPIOKEY_BIT_DIRUP;
 108         if ((input & GPIOKEY_COL2_BITMASK) == 0)
 109                 keybits |= GPIOKEY_BIT_FNRIGHT;
 110
 111         /* query lower row */
 112         gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
 113         input = in_be32(&gpioregs->gpdat);
 114         if ((input & GPIOKEY_COL0_BITMASK) == 0)
 115                 keybits |= GPIOKEY_BIT_DIRLEFT;
 116         if ((input & GPIOKEY_COL1_BITMASK) == 0)
 117                 keybits |= GPIOKEY_BIT_DIRRIGHT;
 118         if ((input & GPIOKEY_COL2_BITMASK) == 0)
 119                 keybits |= GPIOKEY_BIT_DIRDOWN;
 120
 121         /* return bit pattern for keys */
 122         return keybits;
 123 }
 124
 125 /* excerpt from the recovery's hw_info.h */
 126
 127 struct __attribute__ ((__packed__)) eeprom_layout {
 128         char    magic[3];       /** 'ifm' */
 129         u8      len[2];         /** content length without magic/len fields */
 130         u8      version[3];     /** structure version */
 131         u8      type;           /** type of PCB */
 132         u8      reserved[0x37]; /** padding up to offset 0x40 */
 133         u8      macaddress[6];  /** ethernet MAC (for the mainboard) @0x40 */
 134 };
 135
 136 #define HW_COMP_MAINCPU 2
 137
 138 static struct eeprom_layout eeprom_content;
 139 static int eeprom_was_read;     /* has_been_read */
 140 static int eeprom_is_valid;
 141 static int eeprom_version;
 142
 143 #define get_eeprom_field_int(name) ({ \
 144         int value; \
 145         int idx; \
 146         value = 0; \
 147         for (idx = 0; idx < sizeof(name); idx++) { \
 148                 value <<= 8; \
 149                 value |= name[idx]; \
 150         } \
 151         value; \
 152 })
 153
 154 static int read_eeprom(void)
 155 {
 156         int eeprom_datalen;
 157         int ret;
 158
 159         if (eeprom_was_read)
 160                 return 0;
 161
 162         eeprom_is_valid = 0;
 163         ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
 164                         CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
 165                         (uchar *)&eeprom_content, sizeof(eeprom_content));
 166         if (eeprom_diag) {
 167                 printf("DIAG: %s() read rc[%d], size[%d]\n",
 168                         __func__, ret, sizeof(eeprom_content));
 169         }
 170
 171         if (ret != 0)
 172                 return -1;
 173
 174         eeprom_was_read = 1;
 175
 176         /*
 177          * check validity of EEPROM content
 178          * (check version, length, optionally checksum)
 179          */
 180         eeprom_is_valid = 1;
 181         eeprom_datalen = get_eeprom_field_int(eeprom_content.len);
 182         eeprom_version = get_eeprom_field_int(eeprom_content.version);
 183
 184         if (eeprom_diag) {
 185                 printf("DIAG: %s() magic[%c%c%c] len[%d] ver[%d] type[%d]\n",
 186                         __func__, eeprom_content.magic[0],
 187                         eeprom_content.magic[1], eeprom_content.magic[2],
 188                         eeprom_datalen, eeprom_version, eeprom_content.type);
 189         }
 190         if (strncmp(eeprom_content.magic, "ifm", strlen("ifm")) != 0)
 191                 eeprom_is_valid = 0;
 192         if (eeprom_datalen < sizeof(struct eeprom_layout) - 5)
 193                 eeprom_is_valid = 0;
 194         if ((eeprom_version != 1) && (eeprom_version != 2))
 195                 eeprom_is_valid = 0;
 196         if (eeprom_content.type != HW_COMP_MAINCPU)
 197                 eeprom_is_valid = 0;
 198
 199         if (eeprom_diag)
 200                 printf("DIAG: %s() valid[%d]\n", __func__, eeprom_is_valid);
 201
 202         return ret;
 203 }
 204
 205 int mac_read_from_eeprom(void)
 206 {
 207         const u8 *mac;
 208         const char *mac_txt;
 209
 210         if (read_eeprom()) {
 211                 printf("I2C EEPROM read failed.\n");
 212                 return -1;
 213         }
 214
 215         if (!eeprom_is_valid) {
 216                 printf("I2C EEPROM content not valid\n");
 217                 return -1;
 218         }
 219
 220         mac = NULL;
 221         switch (eeprom_version) {
 222         case 1:
 223         case 2:
 224                 mac = (const u8 *)&eeprom_content.macaddress;
 225                 break;
 226         }
 227
 228         if (mac && is_valid_ethaddr(mac)) {
 229                 eth_setenv_enetaddr("ethaddr", mac);
 230                 if (mac_diag) {
 231                         mac_txt = getenv("ethaddr");
 232                         if (mac_txt)
 233                                 printf("DIAG: MAC value [%s]\n", mac_txt);
 234                         else
 235                                 printf("DIAG: failed to setup MAC env\n");
 236                 }
 237         }
 238
 239         return 0;
 240 }
 241
 242 /*
 243  * BEWARE!
 244  * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2
 245  * which the ADS, Aria or PDM360NG boards are using
 246  * (the steps outlined here refer to the Micron datasheet)
 247  */
 248 u32 sdram_init_seq[] = {
 249         /* item 6, at least one NOP after CKE went high */
 250         CONFIG_SYS_DDRCMD_NOP,
 251         CONFIG_SYS_DDRCMD_NOP,
 252         CONFIG_SYS_DDRCMD_NOP,
 253         CONFIG_SYS_DDRCMD_NOP,
 254         CONFIG_SYS_DDRCMD_NOP,
 255         CONFIG_SYS_DDRCMD_NOP,
 256         CONFIG_SYS_DDRCMD_NOP,
 257         CONFIG_SYS_DDRCMD_NOP,
 258         CONFIG_SYS_DDRCMD_NOP,
 259         CONFIG_SYS_DDRCMD_NOP,
 260         /* item 7, precharge all; item 8, tRP (20ns) */
 261         CONFIG_SYS_DDRCMD_PCHG_ALL,
 262         CONFIG_SYS_DDRCMD_NOP,
 263         /* item 9, extended mode register; item 10, tMRD 10ns) */
 264         CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM,
 265         CONFIG_SYS_DDRCMD_NOP,
 266         /*
 267          * item 11, (base) mode register _with_ reset DLL;
 268          * item 12, tMRD (10ns)
 269          */
 270         CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL |
 271         CONFIG_SYS_MICRON_BMODE_PARAM,
 272         CONFIG_SYS_DDRCMD_NOP,
 273         /* item 13, precharge all; item 14, tRP (20ns) */
 274         CONFIG_SYS_DDRCMD_PCHG_ALL,
 275         CONFIG_SYS_DDRCMD_NOP,
 276         /*
 277          * item 15, auto refresh (i.e. refresh with CKE held high);
 278          * item 16, tRFC (70ns)
 279          */
 280         CONFIG_SYS_DDRCMD_RFSH,
 281         CONFIG_SYS_DDRCMD_NOP,
 282         CONFIG_SYS_DDRCMD_NOP,
 283         CONFIG_SYS_DDRCMD_NOP,
 284         CONFIG_SYS_DDRCMD_NOP,
 285         CONFIG_SYS_DDRCMD_NOP,
 286         CONFIG_SYS_DDRCMD_NOP,
 287         CONFIG_SYS_DDRCMD_NOP,
 288         CONFIG_SYS_DDRCMD_NOP,
 289         /*
 290          * item 17, auto refresh (i.e. refresh with CKE held high);
 291          * item 18, tRFC (70ns)
 292          */
 293         CONFIG_SYS_DDRCMD_RFSH,
 294         CONFIG_SYS_DDRCMD_NOP,
 295         CONFIG_SYS_DDRCMD_NOP,
 296         CONFIG_SYS_DDRCMD_NOP,
 297         CONFIG_SYS_DDRCMD_NOP,
 298         CONFIG_SYS_DDRCMD_NOP,
 299         CONFIG_SYS_DDRCMD_NOP,
 300         CONFIG_SYS_DDRCMD_NOP,
 301         CONFIG_SYS_DDRCMD_NOP,
 302         /* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
 303         CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM,
 304         CONFIG_SYS_DDRCMD_NOP,
 305         /*
 306          * item 21, "actually done", but make sure 200 DRAM clock cycles
 307          * have passed after DLL reset before READ requests are issued
 308          * (200 cycles at 160MHz -> 1.25 usec)
 309          */
 310         /* EMPTY, optional, we don't do it */
 311 };
 312
 313 int initdram(void)
 314 {
 315         gd->ram_size = fixed_sdram(NULL, sdram_init_seq,
 316                                    ARRAY_SIZE(sdram_init_seq));
 317
 318         return 0;
 319 }
 320
 321 int misc_init_r(void)
 322 {
 323         u32 keys;
 324         char *s;
 325         int want_recovery;
 326
 327         /* we use bus I2C-0 for the on-board eeprom */
 328         i2c_set_bus_num(0);
 329
 330         /* setup GPIO directions and initial values */
 331         gpio_configure();
 332
 333         /*
 334          * enforce the start of the recovery system when
 335          * - the appropriate keys were pressed
 336          * - "some" external software told us to
 337          * - a previous installation was aborted or has failed
 338          */
 339         want_recovery = 0;
 340         keys = gpio_querykbd();
 341         if (gpio_diag)
 342                 printf("GPIO keyboard status [0x%02X]\n", keys);
 343         if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
 344                 printf("detected recovery request (keyboard)\n");
 345                 want_recovery = 1;
 346         }
 347         s = getenv("want_recovery");
 348         if ((s != NULL) && (*s != '\0')) {
 349                 printf("detected recovery request (environment)\n");
 350                 want_recovery = 1;
 351         }
 352         s = getenv("install_in_progress");
 353         if ((s != NULL) && (*s != '\0')) {
 354                 printf("previous installation has not completed\n");
 355                 want_recovery = 1;
 356         }
 357         s = getenv("install_failed");
 358         if ((s != NULL) && (*s != '\0')) {
 359                 printf("previous installation has failed\n");
 360                 want_recovery = 1;
 361         }
 362         if (want_recovery) {
 363                 printf("enforced start of the recovery system\n");
 364                 setenv("bootcmd", "run recovery");
 365         }
 366
 367         /*
 368          * boot the recovery system without waiting; boot the
 369          * production system without waiting by default, only
 370          * insert a pause (to provide a chance to get a prompt)
 371          * when GPIO keys were pressed during power on
 372          */
 373         if (want_recovery)
 374                 setenv("bootdelay", "0");
 375         else if (!keys)
 376                 setenv("bootdelay", "0");
 377         else
 378                 setenv("bootdelay", "2");
 379
 380         /* get the ethernet MAC from I2C EEPROM */
 381         mac_read_from_eeprom();
 382
 383         return 0;
 384 }
 385
 386 /* setup specific IO pad configuration */
 387 static  iopin_t ioregs_init[] = {
 388         {       /* LPC CS3 */
 389                 offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
 390                 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 391                 IO_PIN_FMUX(1) | IO_PIN_DS(2),
 392         },
 393         {       /* LPC CS1 */
 394                 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
 395                 IO_PIN_OVER_DRVSTR,
 396                 IO_PIN_DS(2),
 397         },
 398         {       /* LPC CS2 */
 399                 offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
 400                 IO_PIN_OVER_DRVSTR,
 401                 IO_PIN_DS(2),
 402         },
 403         {       /* LPC CS4, CS5 */
 404                 offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
 405                 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 406                 IO_PIN_FMUX(1) | IO_PIN_DS(2),
 407         },
 408         {       /* SDHC CLK, CMD, D0, D1, D2, D3 */
 409                 offsetof(struct ioctrl512x, io_control_pata_ior), 6,
 410                 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 411                 IO_PIN_FMUX(1) | IO_PIN_DS(2),
 412         },
 413         {       /* GPIO keyboard */
 414                 offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
 415                 IO_PIN_OVER_FMUX,
 416                 IO_PIN_FMUX(3),
 417         },
 418         {       /* GPIO DN1 PF, LCD power, DN2 PF */
 419                 offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
 420                 IO_PIN_OVER_FMUX,
 421                 IO_PIN_FMUX(3),
 422         },
 423         {       /* GPIO reset AS-i */
 424                 offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
 425                 IO_PIN_OVER_FMUX,
 426                 IO_PIN_FMUX(3),
 427         },
 428         {       /* GPIO reset safety */
 429                 offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
 430                 IO_PIN_OVER_FMUX,
 431                 IO_PIN_FMUX(3),
 432         },
 433         {       /* GPIO reset netX */
 434                 offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
 435                 IO_PIN_OVER_FMUX,
 436                 IO_PIN_FMUX(3),
 437         },
 438         {       /* GPIO ma2 en */
 439                 offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
 440                 IO_PIN_OVER_FMUX,
 441                 IO_PIN_FMUX(3),
 442         },
 443         {       /* GPIO SD CD, SD WP */
 444                 offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
 445                 IO_PIN_OVER_FMUX,
 446                 IO_PIN_FMUX(3),
 447         },
 448         {       /* FEC RX DV */
 449                 offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
 450                 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 451                 IO_PIN_FMUX(2) | IO_PIN_DS(2),
 452         },
 453         {       /* GPIO AS-i prog, AS-i done, LCD backlight */
 454                 offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
 455                 IO_PIN_OVER_FMUX,
 456                 IO_PIN_FMUX(3),
 457         },
 458         {       /* GPIO AS-i wdg */
 459                 offsetof(struct ioctrl512x, io_control_pci_req2), 1,
 460                 IO_PIN_OVER_FMUX,
 461                 IO_PIN_FMUX(3),
 462         },
 463         {       /* GPIO safety wdg */
 464                 offsetof(struct ioctrl512x, io_control_pci_req1), 1,
 465                 IO_PIN_OVER_FMUX,
 466                 IO_PIN_FMUX(3),
 467         },
 468         {       /* GPIO netX wdg */
 469                 offsetof(struct ioctrl512x, io_control_pci_req0), 1,
 470                 IO_PIN_OVER_FMUX,
 471                 IO_PIN_FMUX(3),
 472         },
 473         {       /* GPIO IRQ powerfail */
 474                 offsetof(struct ioctrl512x, io_control_pci_inta), 1,
 475                 IO_PIN_OVER_FMUX,
 476                 IO_PIN_FMUX(3),
 477         },
 478         {       /* GPIO AS-i PWRD */
 479                 offsetof(struct ioctrl512x, io_control_pci_frame), 1,
 480                 IO_PIN_OVER_FMUX,
 481                 IO_PIN_FMUX(3),
 482         },
 483         {       /* GPIO LED0, LED1 */
 484                 offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
 485                 IO_PIN_OVER_FMUX,
 486                 IO_PIN_FMUX(3),
 487         },
 488         {       /* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
 489                 offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
 490                 IO_PIN_OVER_FMUX,
 491                 IO_PIN_FMUX(3),
 492         },
 493         {       /* DIU clk */
 494                 offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
 495                 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 496                 IO_PIN_FMUX(2) | IO_PIN_DS(2),
 497         },
 498         {       /* FEC TX ER, CRS */
 499                 offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
 500                 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 501                 IO_PIN_FMUX(1) | IO_PIN_DS(2),
 502         },
 503         {       /* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */
 504                 offsetof(struct ioctrl512x, io_control_irq0), 1,
 505                 IO_PIN_OVER_FMUX,
 506                 IO_PIN_FMUX(3),
 507         },
 508         {       /*
 509                  * FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
 510                  * rdx 3-0, mdio, rx clk
 511                  */
 512                 offsetof(struct ioctrl512x, io_control_psc0_0), 15,
 513                 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 514                 IO_PIN_FMUX(1) | IO_PIN_DS(2),
 515         },
 516         /* optional: make sure PSC3 remains the serial console */
 517         {       /* LPC CS6 */
 518                 offsetof(struct ioctrl512x, io_control_psc3_4), 1,
 519                 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 520                 IO_PIN_FMUX(1) | IO_PIN_DS(2),
 521         },
 522         /* make sure PSC4 remains available for SPI,
 523             *BUT* PSC4_1 is a GPIO kind of SS! */
 524         {       /* enforce drive strength on the SPI pin */
 525                 offsetof(struct ioctrl512x, io_control_psc4_0), 5,
 526                 IO_PIN_OVER_DRVSTR,
 527                 IO_PIN_DS(2),
 528         },
 529         {
 530                 offsetof(struct ioctrl512x, io_control_psc4_1), 1,
 531                 IO_PIN_OVER_FMUX,
 532                 IO_PIN_FMUX(3),
 533         },
 534         /* optional: make sure PSC5 remains available for SPI */
 535         {       /* enforce drive strength on the SPI pin */
 536                 offsetof(struct ioctrl512x, io_control_psc5_0), 5,
 537                 IO_PIN_OVER_DRVSTR,
 538                 IO_PIN_DS(1),
 539         },
 540         {       /* LPC TSIZ1 */
 541                 offsetof(struct ioctrl512x, io_control_psc6_0), 1,
 542                 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 543                 IO_PIN_FMUX(1) | IO_PIN_DS(2),
 544         },
 545         {       /* DIU hsync */
 546                 offsetof(struct ioctrl512x, io_control_psc6_1), 1,
 547                 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 548                 IO_PIN_FMUX(2) | IO_PIN_DS(1),
 549         },
 550         {       /* DIU vsync */
 551                 offsetof(struct ioctrl512x, io_control_psc6_4), 1,
 552                 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 553                 IO_PIN_FMUX(2) | IO_PIN_DS(1),
 554         },
 555         {       /* PSC7, part of DIU RGB */
 556                 offsetof(struct ioctrl512x, io_control_psc7_0), 2,
 557                 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 558                 IO_PIN_FMUX(2) | IO_PIN_DS(1),
 559         },
 560         {       /* PSC7, safety UART */
 561                 offsetof(struct ioctrl512x, io_control_psc7_2), 2,
 562                 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 563                 IO_PIN_FMUX(0) | IO_PIN_DS(1),
 564         },
 565         {       /* DIU (part of) RGB[] */
 566                 offsetof(struct ioctrl512x, io_control_psc8_3), 16,
 567                 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 568                 IO_PIN_FMUX(2) | IO_PIN_DS(1),
 569         },
 570         {       /* DIU data enable */
 571                 offsetof(struct ioctrl512x, io_control_psc11_4), 1,
 572                 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 573                 IO_PIN_FMUX(2) | IO_PIN_DS(1),
 574         },
 575         /* reduce LPB drive strength for improved EMI */
 576         {       /* LPC OE, LPC RW */
 577                 offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
 578                 IO_PIN_OVER_DRVSTR,
 579                 IO_PIN_DS(2),
 580         },
 581         {       /* LPC AX03 through LPC AD00 */
 582                 offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
 583                 IO_PIN_OVER_DRVSTR,
 584                 IO_PIN_DS(2),
 585         },
 586         {       /* LPC CS5 */
 587                 offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
 588                 IO_PIN_OVER_DRVSTR,
 589                 IO_PIN_DS(2),
 590         },
 591         {       /* SDHC CLK */
 592                 offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
 593                 IO_PIN_OVER_DRVSTR,
 594                 IO_PIN_DS(2),
 595         },
 596         {       /* SDHC DATA */
 597                 offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
 598                 IO_PIN_OVER_DRVSTR,
 599                 IO_PIN_DS(2),
 600         },
 601 };
 602
 603 int checkboard(void)
 604 {
 605         puts("Board: ifm AC14xx\n");
 606
 607         /* initialize function mux & slew rate IO inter alia on IO Pins  */
 608         iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));
 609
 610         return 0;
 611 }
 612
 613 #ifdef CONFIG_OF_BOARD_SETUP
 614 int ft_board_setup(void *blob, bd_t *bd)
 615 {
 616         ft_cpu_setup(blob, bd);
 617
 618         return 0;
 619 }
 620 #endif /* CONFIG_OF_BOARD_SETUP */