board/inka4x0/mt46v32m16-75.h

   1 /*
   2  * Copyright (C) 2007 Semihalf
   3  * Written by Marian Balakowicz <m8@semihalf.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #define SDRAM_DDR       1               /* is DDR */
   9
  10 /* Settings for XLB = 132 MHz */
  11 #define SDRAM_MODE      0x018D0000
  12 #define SDRAM_EMODE     0x40090000
  13 #define SDRAM_CONTROL   0x714F0F00
  14 #define SDRAM_CONFIG1   0x73711930
  15 #define SDRAM_CONFIG2   0x46770000
  16 #define SDRAM_TAPDELAY  0x10000000