board/innokom/lowlevel_init.S

   1 /*
   2  * Most of this taken from Redboot hal_platform_setup.h with cleanup
   3  *
   4  * NOTE: I haven't clean this up considerably, just enough to get it
   5  * running. See hal_platform_setup.h for the source. See
   6  * board/cradle/lowlevel_init.S for another PXA250 setup that is
   7  * much cleaner.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <config.h>
  29 #include <version.h>
  30 #include <asm/arch/pxa-regs.h>
  31
  32 DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
  33
  34 /* wait for coprocessor write complete */
  35    .macro CPWAIT reg
  36    mrc  p15,0,\reg,c2,c0,0
  37    mov  \reg,\reg
  38    sub  pc,pc,#4
  39    .endm
  40
  41 _TEXT_BASE:
  42         .word   CONFIG_SYS_TEXT_BASE
  43
  44
  45 /*
  46  *      Memory setup
  47  */
  48
  49 .globl lowlevel_init
  50 lowlevel_init:
  51
  52     mov      r10, lr
  53
  54         /* Set up GPIO pins first ----------------------------------------- */
  55
  56         ldr             r0,     =GPSR0
  57         ldr             r1,     =CONFIG_SYS_GPSR0_VAL
  58         str             r1,   [r0]
  59
  60         ldr             r0,     =GPSR1
  61         ldr             r1,     =CONFIG_SYS_GPSR1_VAL
  62         str             r1,   [r0]
  63
  64         ldr             r0,     =GPSR2
  65         ldr             r1,     =CONFIG_SYS_GPSR2_VAL
  66         str             r1,   [r0]
  67
  68         ldr             r0,     =GPCR0
  69         ldr             r1,     =CONFIG_SYS_GPCR0_VAL
  70         str             r1,   [r0]
  71
  72         ldr             r0,     =GPCR1
  73         ldr             r1,     =CONFIG_SYS_GPCR1_VAL
  74         str             r1,   [r0]
  75
  76         ldr             r0,     =GPCR2
  77         ldr             r1,     =CONFIG_SYS_GPCR2_VAL
  78         str             r1,   [r0]
  79
  80         ldr             r0,     =GPDR0
  81         ldr             r1,     =CONFIG_SYS_GPDR0_VAL
  82         str             r1,   [r0]
  83
  84         ldr             r0,     =GPDR1
  85         ldr             r1,     =CONFIG_SYS_GPDR1_VAL
  86         str             r1,   [r0]
  87
  88         ldr             r0,     =GPDR2
  89         ldr             r1,     =CONFIG_SYS_GPDR2_VAL
  90         str             r1,   [r0]
  91
  92         ldr             r0,     =GAFR0_L
  93         ldr             r1,     =CONFIG_SYS_GAFR0_L_VAL
  94         str             r1,   [r0]
  95
  96         ldr             r0,     =GAFR0_U
  97         ldr             r1,     =CONFIG_SYS_GAFR0_U_VAL
  98         str             r1,   [r0]
  99
 100         ldr             r0,     =GAFR1_L
 101         ldr             r1,     =CONFIG_SYS_GAFR1_L_VAL
 102         str             r1,   [r0]
 103
 104         ldr             r0,     =GAFR1_U
 105         ldr             r1,     =CONFIG_SYS_GAFR1_U_VAL
 106         str             r1,   [r0]
 107
 108         ldr             r0,     =GAFR2_L
 109         ldr             r1,     =CONFIG_SYS_GAFR2_L_VAL
 110         str             r1,   [r0]
 111
 112         ldr             r0,     =GAFR2_U
 113         ldr             r1,     =CONFIG_SYS_GAFR2_U_VAL
 114         str             r1,   [r0]
 115
 116         ldr     r0,     =PSSR           /* enable GPIO pins */
 117         ldr             r1,     =CONFIG_SYS_PSSR_VAL
 118         str             r1,   [r0]
 119
 120 /*      ldr     r3,     =MSC1           /  low - bank 2 Lubbock Registers / SRAM */
 121 /*      ldr     r2,     =CONFIG_SYS_MSC1_VAL    /  high - bank 3 Ethernet Controller */
 122 /*      str     r2,     [r3]            /  need to set MSC1 before trying to write to the HEX LEDs */
 123 /*      ldr     r2,     [r3]            /  need to read it back to make sure the value latches (see MSC section of manual) */
 124 /* */
 125 /*      ldr     r1,     =LED_BLANK */
 126 /*      mov     r0,     #0xFF */
 127 /*      str     r0,     [r1]            /  turn on hex leds */
 128 /* */
 129 /*loop: */
 130 /* */
 131 /*   ldr        r0, =0xB0070001 */
 132 /*   ldr        r1, =_LED */
 133 /*   str        r0, [r1]                /  hex display */
 134
 135
 136         /* ---------------------------------------------------------------- */
 137         /* Enable memory interface                                          */
 138         /*                                                                  */
 139         /* The sequence below is based on the recommended init steps        */
 140         /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
 141         /* Chapter 10.                                                      */
 142         /* ---------------------------------------------------------------- */
 143
 144         /* ---------------------------------------------------------------- */
 145         /* Step 1: Wait for at least 200 microsedonds to allow internal     */
 146         /*         clocks to settle. Only necessary after hard reset...     */
 147         /*         FIXME: can be optimized later                            */
 148         /* ---------------------------------------------------------------- */
 149
 150         ldr r3, =OSCR                   /* reset the OS Timer Count to zero */
 151         mov r2, #0
 152         str r2, [r3]
 153         ldr r4, =0x300                  /* really 0x2E1 is about 200usec,   */
 154                                         /* so 0x300 should be plenty        */
 155 1:
 156         ldr r2, [r3]
 157         cmp r4, r2
 158         bgt 1b
 159
 160 mem_init:
 161
 162         ldr     r1,  =MEMC_BASE         /* get memory controller base addr. */
 163
 164         /* ---------------------------------------------------------------- */
 165         /* Step 2a: Initialize Asynchronous static memory controller        */
 166         /* ---------------------------------------------------------------- */
 167
 168         /* MSC registers: timing, bus width, mem type                       */
 169
 170         /* MSC0: nCS(0,1)                                                   */
 171         ldr     r2,   =CONFIG_SYS_MSC0_VAL
 172         str     r2,   [r1, #MSC0_OFFSET]
 173         ldr     r2,   [r1, #MSC0_OFFSET]        /* read back to ensure      */
 174                                                 /* that data latches        */
 175         /* MSC1: nCS(2,3)                                                   */
 176         ldr     r2,  =CONFIG_SYS_MSC1_VAL
 177         str     r2,  [r1, #MSC1_OFFSET]
 178         ldr     r2,  [r1, #MSC1_OFFSET]
 179
 180         /* MSC2: nCS(4,5)                                                   */
 181         ldr     r2,  =CONFIG_SYS_MSC2_VAL
 182         str     r2,  [r1, #MSC2_OFFSET]
 183         ldr     r2,  [r1, #MSC2_OFFSET]
 184
 185         /* ---------------------------------------------------------------- */
 186         /* Step 2b: Initialize Card Interface                               */
 187         /* ---------------------------------------------------------------- */
 188
 189         /* MECR: Memory Expansion Card Register                             */
 190         ldr     r2,  =CONFIG_SYS_MECR_VAL
 191         str     r2,  [r1, #MECR_OFFSET]
 192         ldr     r2,     [r1, #MECR_OFFSET]
 193
 194         /* MCMEM0: Card Interface slot 0 timing                             */
 195         ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
 196         str     r2,  [r1, #MCMEM0_OFFSET]
 197         ldr     r2,     [r1, #MCMEM0_OFFSET]
 198
 199         /* MCMEM1: Card Interface slot 1 timing                             */
 200         ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
 201         str     r2,  [r1, #MCMEM1_OFFSET]
 202         ldr     r2,     [r1, #MCMEM1_OFFSET]
 203
 204         /* MCATT0: Card Interface Attribute Space Timing, slot 0            */
 205         ldr     r2,  =CONFIG_SYS_MCATT0_VAL
 206         str     r2,  [r1, #MCATT0_OFFSET]
 207         ldr     r2,     [r1, #MCATT0_OFFSET]
 208
 209         /* MCATT1: Card Interface Attribute Space Timing, slot 1            */
 210         ldr     r2,  =CONFIG_SYS_MCATT1_VAL
 211         str     r2,  [r1, #MCATT1_OFFSET]
 212         ldr     r2,     [r1, #MCATT1_OFFSET]
 213
 214         /* MCIO0: Card Interface I/O Space Timing, slot 0                   */
 215         ldr     r2,  =CONFIG_SYS_MCIO0_VAL
 216         str     r2,  [r1, #MCIO0_OFFSET]
 217         ldr     r2,     [r1, #MCIO0_OFFSET]
 218
 219         /* MCIO1: Card Interface I/O Space Timing, slot 1                   */
 220         ldr     r2,  =CONFIG_SYS_MCIO1_VAL
 221         str     r2,  [r1, #MCIO1_OFFSET]
 222         ldr     r2,     [r1, #MCIO1_OFFSET]
 223
 224         /* ---------------------------------------------------------------- */
 225         /* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
 226         /* ---------------------------------------------------------------- */
 227
 228         /* test if we run from flash or RAM - RAM/BDI: don't setup RAM      */
 229         adr     r3, mem_init            /* r0 <- current position of code   */
 230         ldr     r2, =mem_init
 231         cmp     r3, r2                  /* skip init if in place            */
 232         beq     initirqs
 233
 234
 235         /* ---------------------------------------------------------------- */
 236         /* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
 237         /* ---------------------------------------------------------------- */
 238
 239         /* Before accessing MDREFR we need a valid DRI field, so we set     */
 240         /* this to power on defaults + DRI field.                           */
 241
 242         ldr     r3,     =CONFIG_SYS_MDREFR_VAL
 243         ldr     r2,     =0xFFF
 244         and     r3,     r3, r2
 245         ldr     r4,     =0x03ca4000
 246         orr     r4,     r4,  r3
 247
 248         str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
 249         ldr     r4,     [r1, #MDREFR_OFFSET]
 250
 251
 252         /* ---------------------------------------------------------------- */
 253         /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
 254         /* ---------------------------------------------------------------- */
 255
 256         /* Initialize SXCNFG register. Assert the enable bits               */
 257
 258         /* Write SXMRS to cause an MRS command to all enabled banks of      */
 259         /* synchronous static memory. Note that SXLCR need not be written   */
 260         /* at this time.                                                    */
 261
 262         /* FIXME: we use async mode for now                                 */
 263
 264
 265         /* ---------------------------------------------------------------- */
 266         /* Step 4: Initialize SDRAM                                         */
 267         /* ---------------------------------------------------------------- */
 268
 269         /* Step 4a: assert MDREFR:K?RUN and configure                       */
 270         /*          MDREFR:K1DB2 and MDREFR:K2DB2 as desired.               */
 271
 272         ldr     r4,     =CONFIG_SYS_MDREFR_VAL
 273         str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
 274         ldr     r4,     [r1, #MDREFR_OFFSET]
 275
 276         /* Step 4b: de-assert MDREFR:SLFRSH.                                */
 277
 278         bic     r4,     r4, #(MDREFR_SLFRSH)
 279
 280         str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
 281         ldr     r4,     [r1, #MDREFR_OFFSET]
 282
 283
 284         /* Step 4c: assert MDREFR:E1PIN and E0PIO                           */
 285
 286         orr     r4,     r4,     #(MDREFR_E1PIN|MDREFR_E0PIN)
 287
 288         str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
 289         ldr     r4,     [r1, #MDREFR_OFFSET]
 290
 291
 292         /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
 293         /*          configure but not enable each SDRAM partition pair.     */
 294
 295         ldr     r4,     =CONFIG_SYS_MDCNFG_VAL
 296         bic     r4,     r4,     #(MDCNFG_DE0|MDCNFG_DE1)
 297
 298         str     r4,     [r1, #MDCNFG_OFFSET]    /* write back MDCNFG        */
 299         ldr     r4,     [r1, #MDCNFG_OFFSET]
 300
 301
 302         /* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
 303         /*          100..200 µsec.                                          */
 304
 305         ldr r3, =OSCR                   /* reset the OS Timer Count to zero */
 306         mov r2, #0
 307         str r2, [r3]
 308         ldr r4, =0x300                  /* really 0x2E1 is about 200usec,   */
 309                                         /* so 0x300 should be plenty        */
 310 1:
 311         ldr r2, [r3]
 312         cmp r4, r2
 313         bgt 1b
 314
 315
 316         /* Step 4f: Trigger a number (usually 8) refresh cycles by          */
 317         /*          attempting non-burst read or write accesses to disabled */
 318         /*          SDRAM, as commonly specified in the power up sequence   */
 319         /*          documented in SDRAM data sheets. The address(es) used   */
 320         /*          for this purpose must not be cacheable.                 */
 321
 322         /*          There should 9 writes, since the first write doesn't    */
 323         /*          trigger a refresh cycle on PXA250. See Intel PXA250 and */
 324         /*          PXA210 Processors Specification Update,                 */
 325         /*          Jan 2003, Errata #116, page 30.                         */
 326
 327
 328         ldr     r3,     =CONFIG_SYS_DRAM_BASE
 329         str     r2, [r3]
 330         str     r2, [r3]
 331         str     r2, [r3]
 332         str     r2, [r3]
 333         str     r2, [r3]
 334         str     r2, [r3]
 335         str     r2, [r3]
 336         str     r2, [r3]
 337         str     r2, [r3]
 338
 339         /* Step 4g: Write MDCNFG with enable bits asserted                  */
 340         /*          (MDCNFG:DEx set to 1).                                  */
 341
 342         ldr     r3, [r1, #MDCNFG_OFFSET]
 343         orr     r3,     r3,     #(MDCNFG_DE0|MDCNFG_DE1)
 344         str     r3, [r1, #MDCNFG_OFFSET]
 345
 346         /* Step 4h: Write MDMRS.                                            */
 347
 348         ldr     r2,  =CONFIG_SYS_MDMRS_VAL
 349         str     r2,  [r1, #MDMRS_OFFSET]
 350
 351
 352         /* We are finished with Intel's memory controller initialisation    */
 353
 354         /* ---------------------------------------------------------------- */
 355         /* Disable (mask) all interrupts at interrupt controller            */
 356         /* ---------------------------------------------------------------- */
 357
 358 initirqs:
 359
 360         mov     r1, #0          /* clear int. level register (IRQ, not FIQ) */
 361         ldr     r2,  =ICLR
 362         str     r1,  [r2]
 363
 364         ldr     r2,  =ICMR      /* mask all interrupts at the controller    */
 365         str     r1,  [r2]
 366
 367
 368         /* ---------------------------------------------------------------- */
 369         /* Clock initialisation                                             */
 370         /* ---------------------------------------------------------------- */
 371
 372 initclks:
 373
 374         /* Disable the peripheral clocks, and set the core clock frequency  */
 375         /* (hard-coding at 398.12MHz for now).                              */
 376
 377         /* Turn Off ALL on-chip peripheral clocks for re-configuration      */
 378         /* Note: See label 'ENABLECLKS' for the re-enabling                 */
 379         ldr     r1,  =CKEN
 380         mov     r2,  #0
 381         str     r2,  [r1]
 382
 383
 384         /* default value in case no valid rotary switch setting is found    */
 385         ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
 386
 387         /* ... and write the core clock config register                     */
 388         ldr     r1,  =CCCR
 389         str     r2,  [r1]
 390
 391         /* enable the 32Khz oscillator for RTC and PowerManager             */
 392 /*
 393         ldr     r1,  =OSCC
 394         mov     r2,  #OSCC_OON
 395         str     r2,  [r1]
 396 */
 397         /* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
 398         /* has settled.                                                     */
 399 60:
 400         ldr     r2, [r1]
 401         ands    r2, r2, #1
 402         beq     60b
 403
 404         /* ---------------------------------------------------------------- */
 405         /*                                                                  */
 406         /* ---------------------------------------------------------------- */
 407
 408         /* Save SDRAM size                                                  */
 409         ldr     r1, =DRAM_SIZE
 410         str     r8, [r1]
 411
 412         /* Interrupt init: Mask all interrupts                              */
 413         ldr     r0, =ICMR                       /* enable no sources        */
 414         mov     r1, #0
 415         str     r1, [r0]
 416
 417         /* FIXME */
 418
 419 #ifndef DEBUG
 420         /*Disable software and data breakpoints */
 421         mov     r0,#0
 422         mcr     p15,0,r0,c14,c8,0  /* ibcr0 */
 423         mcr     p15,0,r0,c14,c9,0  /* ibcr1 */
 424         mcr     p15,0,r0,c14,c4,0  /* dbcon */
 425
 426         /*Enable all debug functionality */
 427         mov     r0,#0x80000000
 428         mcr     p14,0,r0,c10,c0,0  /* dcsr */
 429 #endif
 430
 431         /* ---------------------------------------------------------------- */
 432         /* End lowlevel_init                                                     */
 433         /* ---------------------------------------------------------------- */
 434
 435 endlowlevel_init:
 436
 437     mov     pc, lr