board/integratorcp/platform.S

   1 /*
   2  * Board specific setup info
   3  *
   4  * (C) Copyright 2003, ARM Ltd.
   5  * Philippe Robin, <philippe.robin@arm.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <config.h>
  27 #include <version.h>
  28
  29 /* Reset using CM control register */
  30 .global reset_cpu
  31 reset_cpu:
  32         mov     r0, #CM_BASE
  33         ldr     r1,[r0,#OS_CTRL]
  34         orr     r1,r1,#CMMASK_RESET
  35         str     r1,[r0,#OS_CTRL]
  36
  37 reset_failed:
  38         b       reset_failed
  39
  40 /* set up the platform, once the cpu has been initialized */
  41 .globl platformsetup
  42 platformsetup:
  43         /* If U-Boot has been run after the ARM boot monitor
  44          * then all the necessary actions have been done
  45          * otherwise we are running from user flash mapped to 0x00000000
  46          * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
  47          * Changes to the (possibly soft) reset defaults of the processor
  48          * itself should be performed in cpu/arm<>/start.S
  49          * This function affects only the core module or board settings
  50          */
  51
  52 #ifdef CONFIG_CM_INIT
  53         /* CM has an initialization register
  54          * - bits in it are wired into test-chip pins to force
  55          *   reset defaults
  56          * - may need to change its contents for U-Boot
  57          */
  58
  59         /* set the desired CM specific value */
  60         mov     r2,#CMMASK_LOWVEC       /* Vectors at 0x00000000 for all */
  61
  62 #if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
  63         orr     r2,r2,#CMMASK_INIT_102
  64 #else
  65
  66 #if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
  67     !defined (CONFIG_CM940T)
  68     /* CMxx6 code */
  69
  70 #ifdef  CONFIG_CM_MULTIPLE_SSRAM
  71         /* set simple mapping             */
  72         and     r2,r2,#CMMASK_MAP_SIMPLE
  73 #endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */
  74
  75 #ifdef  CONFIG_CM_TCRAM
  76         /* disable TCRAM                  */
  77         and     r2,r2,#CMMASK_TCRAM_DISABLE
  78 #endif /* #ifdef CONFIG_CM_TCRAM          */
  79
  80 #if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
  81             defined (CONFIG_CM1136JF_S)
  82
  83         and     r2,r2,#CMMASK_LE
  84
  85 #endif /* cpu with little endian initialization */
  86
  87         orr     r2,r2,#CMMASK_CMxx6_COMMON
  88
  89 #endif /* CMxx6 code */
  90
  91 #endif /* ARM102xxE value */
  92
  93         /* read CM_INIT    */
  94         mov     r0, #CM_BASE
  95         ldr     r1, [r0, #OS_INIT]
  96         /* check against desired bit setting */
  97         and     r3,r1,r2
  98         cmp     r3,r2
  99         beq     init_reg_OK
 100
 101         /* lock for change */
 102         mov     r3, #CMVAL_LOCK1
 103         and     r3, r3, #CMVAL_LOCK2
 104         str     r3, [r0, #OS_LOCK]
 105         /* set desired value */
 106         orr     r1,r1,r2
 107         /* write & relock CM_INIT */
 108         str     r1, [r0, #OS_INIT]
 109         mov     r1, #CMVAL_UNLOCK
 110         str     r1, [r0, #OS_LOCK]
 111
 112         /* soft reset so new values used */
 113         b       reset_cpu
 114
 115 init_reg_OK:
 116
 117 #endif /* CONFIG_CM_INIT */
 118
 119         mov     pc, lr
 120
 121 #ifdef  CONFIG_CM_SPD_DETECT
 122         /* Fast memory is available for the DRAM data
 123          * - ensure it has been transferred, then summarize the data
 124          *   into a CM register
 125          */
 126 .globl dram_query
 127 dram_query:
 128         stmfd   r13!,{r4-r6,lr}
 129         /* set up SDRAM info                              */
 130         /* - based on example code from the CM User Guide */
 131         mov     r0, #CM_BASE
 132
 133 readspdbit:
 134         ldr     r1, [r0, #OS_SDRAM]     /* read the SDRAM register */
 135         and     r1, r1, #0x20           /* mask SPD bit (5)        */
 136         cmp     r1, #0x20               /* test if set             */
 137         bne     readspdbit
 138
 139 setupsdram:
 140         add     r0, r0, #OS_SPD         /* address the copy of the SDP data */
 141         ldrb    r1, [r0, #3]            /* number of row address lines      */
 142         ldrb    r2, [r0, #4]            /* number of column address lines   */
 143         ldrb    r3, [r0, #5]            /* number of banks                  */
 144         ldrb    r4, [r0, #31]           /* module bank density              */
 145         mul     r5, r4, r3              /* size of SDRAM (MB divided by 4)  */
 146         mov     r5, r5, ASL#2           /* size in MB                       */
 147         mov     r0, #CM_BASE            /* reload for later code            */
 148         cmp     r5, #0x10               /* is it 16MB?                      */
 149         bne     not16
 150         mov     r6, #0x2                /* store size and CAS latency of 2  */
 151         b       writesize
 152
 153 not16:
 154         cmp     r5, #0x20               /* is it  32MB? */
 155         bne     not32
 156         mov     r6, #0x6
 157         b       writesize
 158
 159 not32:
 160         cmp     r5, #0x40               /* is it  64MB? */
 161         bne     not64
 162         mov     r6, #0xa
 163         b       writesize
 164
 165 not64:
 166         cmp     r5, #0x80               /* is it 128MB? */
 167         bne     not128
 168         mov     r6, #0xe
 169         b       writesize
 170
 171 not128:
 172         /* if it is none of these sizes then it is either 256MB, or
 173          * there is no SDRAM fitted so default to 256MB
 174          */
 175         mov     r6, #0x12
 176
 177 writesize:
 178         mov     r1, r1, ASL#8           /* row addr lines from SDRAM reg */
 179         orr     r2, r1, r2, ASL#12      /* OR in column address lines    */
 180         orr     r3, r2, r3, ASL#16      /* OR in number of banks         */
 181         orr     r6, r6, r3              /* OR in size and CAS latency    */
 182         str     r6, [r0, #OS_SDRAM]     /* store SDRAM parameters        */
 183
 184 #endif /* #ifdef CONFIG_CM_SPD_DETECT */
 185
 186         ldmfd   r13!,{r4-r6,pc}                 /* back to caller */
 187
 188 #ifdef  CONFIG_CM_REMAP
 189         /* CM remap bit is operational
 190          * - use it to map writeable memory at 0x00000000, in place of flash
 191          */
 192 .globl cm_remap
 193 cm_remap:
 194         stmfd   r13!,{r4-r10,lr}
 195
 196         mov     r0, #CM_BASE
 197         ldr     r1, [r0, #OS_CTRL]
 198         orr     r1, r1, #CMMASK_REMAP   /* set remap and led bits */
 199         str     r1, [r0, #OS_CTRL]
 200
 201         /* Now 0x00000000 is writeable, replace the vectors  */
 202         ldr     r0, =_start     /* r0 <- start of vectors           */
 203         ldr     r2, =_armboot_start     /* r2 <- past vectors               */
 204         sub     r1,r1,r1                /* destination 0x00000000           */
 205
 206 copy_vec:
 207         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 208         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 209         cmp     r0, r2                  /* until source end address [r2]    */
 210         ble     copy_vec
 211
 212         ldmfd   r13!,{r4-r10,pc}        /* back to caller                   */
 213
 214 #endif /* #ifdef CONFIG_CM_REMAP */