board/intel/galileo/galileo.c

   1 /*
   2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/device.h>
  10 #include <asm/arch/quark.h>
  11
  12 int board_early_init_f(void)
  13 {
  14         return 0;
  15 }
  16
  17 /*
  18  * Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin.
  19  *
  20  * We cannot use any public GPIO APIs in <asm-generic/gpio.h> to control this
  21  * pin, as these APIs will eventually call into gpio_ich6_ofdata_to_platdata()
  22  * in the Intel ICH6 GPIO driver where it calls PCI configuration space access
  23  * APIs which will trigger PCI enumeration process.
  24  *
  25  * Check <asm/arch-quark/quark.h> for more details.
  26  */
  27 void board_assert_perst(void)
  28 {
  29         u32 base, port, val;
  30
  31         /* retrieve the GPIO IO base */
  32         qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base);
  33         base = (base & 0xffff) & ~0x7f;
  34
  35         /* enable the pin */
  36         port = base + 0x20;
  37         val = inl(port);
  38         val |= (1 << 0);
  39         outl(val, port);
  40
  41         /* configure the pin as output */
  42         port = base + 0x24;
  43         val = inl(port);
  44         val &= ~(1 << 0);
  45         outl(val, port);
  46
  47         /* pull it down (assert) */
  48         port = base + 0x28;
  49         val = inl(port);
  50         val &= ~(1 << 0);
  51         outl(val, port);
  52 }
  53
  54 void board_deassert_perst(void)
  55 {
  56         u32 base, port, val;
  57
  58         /* retrieve the GPIO IO base */
  59         qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base);
  60         base = (base & 0xffff) & ~0x7f;
  61
  62         /* pull it up (de-assert) */
  63         port = base + 0x28;
  64         val = inl(port);
  65         val |= (1 << 0);
  66         outl(val, port);
  67 }