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git.ipfire.org Git - people/ms/u-boot.git/blob - board/intercontrol/digsy_mtc/digsy_mtc.c
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2005-2009
9 * Modified for InterControl digsyMTC MPC5200 board by
10 * Frank Bodammer, GCD Hard- & Software GmbH,
11 * frank.bodammer@gcd-solutions.de
14 * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
16 * SPDX-License-Identifier: GPL-2.0+
23 #include <asm/processor.h>
26 #if defined(CONFIG_DIGSY_REV5)
27 #include "is45s16800a2.h"
28 #include <mtd/cfi_flash.h>
31 #include "is42s16800a-7t.h"
34 #include <fdt_support.h>
38 DECLARE_GLOBAL_DATA_PTR
;
40 extern int usb_cpu_init(void);
42 #if defined(CONFIG_DIGSY_REV5)
44 * The M29W128GH needs a special reset command function,
45 * details see the doc/README.cfi file
47 void flash_cmd_reset(flash_info_t
*info
)
49 flash_write_cmd(info
, 0, 0, AMD_CMD_RESET
);
53 #ifndef CONFIG_SYS_RAMBOOT
54 static void sdram_start(int hi_addr
)
56 long hi_addr_bit
= hi_addr
? 0x01000000 : 0;
57 long control
= SDRAM_CONTROL
| hi_addr_bit
;
59 /* unlock mode register */
60 out_be32((void *)MPC5XXX_SDRAM_CTRL
, control
| 0x80000000);
62 /* precharge all banks */
63 out_be32((void *)MPC5XXX_SDRAM_CTRL
, control
| 0x80000002);
66 out_be32((void *)MPC5XXX_SDRAM_CTRL
, control
| 0x80000004);
68 /* set mode register */
69 out_be32((void *)MPC5XXX_SDRAM_MODE
, SDRAM_MODE
);
71 /* normal operation */
72 out_be32((void *)MPC5XXX_SDRAM_CTRL
, control
);
77 * ATTENTION: Although partially referenced initdram does NOT make real use
78 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
79 * CONFIG_SYS_SDRAM_BASE is something other than 0x00000000.
87 #ifndef CONFIG_SYS_RAMBOOT
90 /* setup SDRAM chip selects */
91 out_be32((void *)MPC5XXX_SDRAM_CS0CFG
, 0x0000001C); /* 512MB at 0x0 */
92 out_be32((void *)MPC5XXX_SDRAM_CS1CFG
, 0x80000000); /* disabled */
94 /* setup config registers */
95 out_be32((void *)MPC5XXX_SDRAM_CONFIG1
, SDRAM_CONFIG1
);
96 out_be32((void *)MPC5XXX_SDRAM_CONFIG2
, SDRAM_CONFIG2
);
98 /* find RAM size using SDRAM CS0 only */
100 test1
= get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
, 0x08000000);
102 test2
= get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
, 0x08000000);
110 /* memory smaller than 1MB is impossible */
111 if (dramsize
< (1 << 20))
114 /* set SDRAM CS0 size according to the amount of RAM found */
116 out_be32((void *)MPC5XXX_SDRAM_CS0CFG
,
117 (0x13 + __builtin_ffs(dramsize
>> 20) - 1));
119 out_be32((void *)MPC5XXX_SDRAM_CS0CFG
, 0); /* disabled */
122 /* let SDRAM CS1 start right after CS0 */
123 out_be32((void *)MPC5XXX_SDRAM_CS1CFG
, dramsize
+ 0x0000001C);
125 /* find RAM size using SDRAM CS1 only */
126 test1
= get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE
+ dramsize
),
130 /* memory smaller than 1MB is impossible */
131 if (dramsize2
< (1 << 20))
134 /* set SDRAM CS1 size according to the amount of RAM found */
136 out_be32((void *)MPC5XXX_SDRAM_CS1CFG
, (dramsize
|
137 (0x13 + __builtin_ffs(dramsize2
>> 20) - 1)));
139 out_be32((void *)MPC5XXX_SDRAM_CS1CFG
, dramsize
); /* disabled */
142 #else /* CONFIG_SYS_RAMBOOT */
144 /* retrieve size of memory connected to SDRAM CS0 */
145 dramsize
= in_be32((void *)MPC5XXX_SDRAM_CS0CFG
) & 0xFF;
146 if (dramsize
>= 0x13)
147 dramsize
= (1 << (dramsize
- 0x13)) << 20;
151 /* retrieve size of memory connected to SDRAM CS1 */
152 dramsize2
= in_be32((void *)MPC5XXX_SDRAM_CS1CFG
) & 0xFF;
153 if (dramsize2
>= 0x13)
154 dramsize2
= (1 << (dramsize2
- 0x13)) << 20;
158 #endif /* CONFIG_SYS_RAMBOOT */
161 * On MPC5200B we need to set the special configuration delay in the
162 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
163 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
165 * "The SDelay should be written to a value of 0x00000004. It is
166 * required to account for changes caused by normal wafer processing
171 if ((SVR_MJREV(svr
) >= 2) &&
172 (PVR_MAJ(pvr
) == 1) && (PVR_MIN(pvr
) == 4))
173 out_be32((void *)MPC5XXX_SDRAM_SDELAY
, 0x04);
175 gd
->ram_size
= dramsize
+ dramsize2
;
183 int i
= getenv_f("serial#", buf
, sizeof(buf
));
185 puts ("Board: InterControl digsyMTC");
186 #if defined(CONFIG_DIGSY_REV5)
198 #if defined(CONFIG_VIDEO)
200 #define GPIO_USB1_0 0x00010000 /* Power-On pin */
201 #define GPIO_USB1_9 0x08 /* PX_~EN pin */
203 #define GPIO_EE_DO 0x10 /* PSC6_0 (DO) pin */
204 #define GPIO_EE_CTS 0x20 /* PSC6_1 (CTS) pin */
205 #define GPIO_EE_DI 0x10000000 /* PSC6_2 (DI) pin */
206 #define GPIO_EE_CLK 0x20000000 /* PSC6_3 (CLK) pin */
208 #define GPT_GPIO_ON 0x00000034 /* GPT as simple GPIO, high */
210 static void exbo_hw_init(void)
212 struct mpc5xxx_gpt
*gpt
= (struct mpc5xxx_gpt
*)MPC5XXX_GPT
;
213 struct mpc5xxx_gpio
*gpio
= (struct mpc5xxx_gpio
*)MPC5XXX_GPIO
;
214 struct mpc5xxx_wu_gpio
*wu_gpio
=
215 (struct mpc5xxx_wu_gpio
*)MPC5XXX_WU_GPIO
;
217 /* configure IrDA pins (PSC6 port) as gpios */
218 gpio
->port_config
&= 0xFF8FFFFF;
220 /* Init for USB1_0, EE_CLK and EE_DI - Low */
221 setbits_be32(&gpio
->simple_ddr
,
222 GPIO_USB1_0
| GPIO_EE_CLK
| GPIO_EE_DI
);
223 clrbits_be32(&gpio
->simple_ode
,
224 GPIO_USB1_0
| GPIO_EE_CLK
| GPIO_EE_DI
);
225 clrbits_be32(&gpio
->simple_dvo
,
226 GPIO_USB1_0
| GPIO_EE_CLK
| GPIO_EE_DI
);
227 setbits_be32(&gpio
->simple_gpioe
,
228 GPIO_USB1_0
| GPIO_EE_CLK
| GPIO_EE_DI
);
230 /* Init for EE_DO, EE_CTS - Input */
231 clrbits_8(&wu_gpio
->ddr
, GPIO_EE_DO
| GPIO_EE_CTS
);
232 setbits_8(&wu_gpio
->enable
, GPIO_EE_DO
| GPIO_EE_CTS
);
234 /* Init for PX_~EN (USB1_9) - High */
235 clrbits_8(&gpio
->sint_ode
, GPIO_USB1_9
);
236 setbits_8(&gpio
->sint_ddr
, GPIO_USB1_9
);
237 clrbits_8(&gpio
->sint_inten
, GPIO_USB1_9
);
238 setbits_8(&gpio
->sint_dvo
, GPIO_USB1_9
);
239 setbits_8(&gpio
->sint_gpioe
, GPIO_USB1_9
);
241 /* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */
242 out_be32(&gpt
[0].emsr
, GPT_GPIO_ON
);
243 /* Init for S Switch (GPIO4) - Timer_1 GPIO High */
244 out_be32(&gpt
[1].emsr
, GPT_GPIO_ON
);
246 /* Power-On camera supply */
247 setbits_be32(&gpio
->simple_dvo
, GPIO_USB1_0
);
250 static inline void exbo_hw_init(void) {}
251 #endif /* CONFIG_VIDEO */
253 int board_early_init_r(void)
256 * Now, when we are in RAM, enable flash write access for detection
257 * process. Note that CS_BOOT cannot be cleared when executing in
260 /* disable CS_BOOT */
261 clrbits_be32((void *)MPC5XXX_ADDECR
, (1 << 25));
263 setbits_be32((void *)MPC5XXX_ADDECR
, (1 << 17));
265 setbits_be32((void *)MPC5XXX_ADDECR
, (1 << 16));
267 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
268 /* Low level USB init, required for proper kernel operation */
275 void board_get_enetaddr (uchar
* enet
)
278 ushort addr_of_eth_addr
= 0;
280 ushort len_sys_cfg
= 0;
282 /* check identification word */
283 eeprom_read(EEPROM_ADDR
, EEPROM_ADDR_IDENT
, (uchar
*)&read
, 2);
284 if (read
!= EEPROM_IDENT
)
287 /* calculate offset of config area */
288 eeprom_read(EEPROM_ADDR
, EEPROM_ADDR_LEN_SYS
, (uchar
*)&len_sys
, 2);
289 eeprom_read(EEPROM_ADDR
, EEPROM_ADDR_LEN_SYSCFG
,
290 (uchar
*)&len_sys_cfg
, 2);
291 addr_of_eth_addr
= (len_sys
+ len_sys_cfg
+ EEPROM_ADDR_ETHADDR
) << 1;
292 if (addr_of_eth_addr
>= EEPROM_LEN
)
295 eeprom_read(EEPROM_ADDR
, addr_of_eth_addr
, enet
, 6);
298 int misc_init_r(void)
303 /* check if graphic extension board is present */
304 devbusfn
= pci_find_device(PCI_VENDOR_ID_FUJITSU
,
305 PCI_DEVICE_ID_CORAL_PA
, 0);
309 if (!eth_getenv_enetaddr("ethaddr", enetaddr
)) {
310 board_get_enetaddr(enetaddr
);
311 eth_setenv_enetaddr("ethaddr", enetaddr
);
318 static struct pci_controller hose
;
320 extern void pci_mpc5xxx_init(struct pci_controller
*);
322 void pci_init_board(void)
324 pci_mpc5xxx_init(&hose
);
328 #ifdef CONFIG_CMD_IDE
330 #ifdef CONFIG_IDE_RESET
332 void init_ide_reset(void)
334 debug ("init_ide_reset\n");
336 /* set gpio output value to 1 */
337 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O
, (1 << 25));
338 /* open drain output */
339 setbits_be32((void *)MPC5XXX_WU_GPIO_ODE
, (1 << 25));
340 /* direction output */
341 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR
, (1 << 25));
343 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE
, (1 << 25));
347 void ide_set_reset(int idereset
)
349 debug ("ide_reset(%d)\n", idereset
);
351 /* set gpio output value to 0 */
352 clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O
, (1 << 25));
353 /* open drain output */
354 setbits_be32((void *)MPC5XXX_WU_GPIO_ODE
, (1 << 25));
355 /* direction output */
356 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR
, (1 << 25));
358 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE
, (1 << 25));
362 /* set gpio output value to 1 */
363 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O
, (1 << 25));
364 /* open drain output */
365 setbits_be32((void *)MPC5XXX_WU_GPIO_ODE
, (1 << 25));
366 /* direction output */
367 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR
, (1 << 25));
369 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE
, (1 << 25));
371 #endif /* CONFIG_IDE_RESET */
372 #endif /* CONFIG_CMD_IDE */
374 #ifdef CONFIG_OF_BOARD_SETUP
375 static void ft_delete_node(void *fdt
, const char *compat
)
380 off
= fdt_node_offset_by_compatible(fdt
, -1, compat
);
382 printf("Could not find %s node.\n", compat
);
386 ret
= fdt_del_node(fdt
, off
);
388 printf("Could not delete %s node.\n", compat
);
390 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
391 static void ft_adapt_flash_base(void *blob
)
393 flash_info_t
*dev
= &flash_info
[0];
395 struct fdt_property
*prop
;
399 off
= fdt_node_offset_by_compatible(blob
, -1, "fsl,mpc5200b-lpb");
401 printf("Could not find fsl,mpc5200b-lpb node.\n");
405 /* found compatible property */
406 prop
= fdt_get_property_w(blob
, off
, "ranges", &len
);
408 reg
= reg2
= (u32
*)&prop
->data
[0];
410 reg
[2] = dev
->start
[0];
412 fdt_setprop(blob
, off
, "ranges", reg2
, len
);
414 printf("Could not find ranges\n");
417 extern ulong
flash_get_size (phys_addr_t base
, int banknum
);
419 /* Update the Flash Baseaddr settings */
420 int update_flash_size (int flash_size
)
422 volatile struct mpc5xxx_mmap_ctl
*mm
=
423 (struct mpc5xxx_mmap_ctl
*) CONFIG_SYS_MBAR
;
427 unsigned long base
= 0x0;
428 u32
*cs_reg
= (u32
*)&mm
->cs0_start
;
430 for (i
= 0; i
< 2; i
++) {
431 dev
= &flash_info
[i
];
434 /* calculate new base addr for this chipselect */
436 out_be32(cs_reg
, START_REG(base
));
438 out_be32(cs_reg
, STOP_REG(base
, dev
->size
));
440 /* recalculate the sectoraddr in the cfi driver */
441 size
+= flash_get_size(base
, i
);
444 flash_protect_default();
445 gd
->bd
->bi_flashstart
= base
;
448 #endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
450 int ft_board_setup(void *blob
, bd_t
*bd
)
452 int phy_addr
= CONFIG_PHY_ADDR
;
453 char eth_path
[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
455 ft_cpu_setup(blob
, bd
);
457 * There are 2 RTC nodes in the DTS, so remove
458 * the unneeded node here.
460 #if defined(CONFIG_DIGSY_REV5)
461 ft_delete_node(blob
, "dallas,ds1339");
463 ft_delete_node(blob
, "mc,rv3029c2");
465 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
466 #ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
467 /* Update reg property in all nor flash nodes too */
468 fdt_fixup_nor_flash_size(blob
);
470 ft_adapt_flash_base(blob
);
472 /* fix up the phy address */
473 do_fixup_by_path(blob
, eth_path
, "reg", &phy_addr
, sizeof(int), 0);
477 #endif /* CONFIG_OF_BOARD_SETUP */