board/iphase4539/iphase4539.c

   1 /*
   2  * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <ioports.h>
   9 #include <mpc8260.h>
  10 #include <asm/io.h>
  11 #include <asm/immap_8260.h>
  12
  13 int hwc_flash_size (void);
  14 int hwc_local_sdram_size (void);
  15 int hwc_main_sdram_size (void);
  16 int hwc_serial_number (void);
  17 int hwc_mac_address (char *str);
  18 int hwc_manufact_date (char *str);
  19 int seeprom_read (int addr, uchar * data, int size);
  20
  21 /*
  22  * I/O Port configuration table
  23  *
  24  * if conf is 1, then that port pin will be configured at boot time
  25  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  26  *
  27  * The port definitions are taken from the old firmware (see
  28  * also SYS/H/4539.H):
  29  *
  30  *        ppar      psor        pdir       podr       pdat
  31  * PA: 0x02ffffff 0x02c00000 0xfc403fe6 0x00000000 0x02403fc0
  32  * PB: 0x0fffdeb0 0x000000b0 0x0f032347 0x00000000 0x0f000290
  33  * PC: 0x030ffa55 0x030f0040 0xbcf005ea 0x00000000 0xc0c0ba7d
  34  * PD: 0x09c04e3c 0x01000e3c 0x0a7ff1c3 0x00000000 0x00ce0ae9
  35  */
  36 const iop_conf_t iop_conf_tab[4][32] = {
  37
  38         /* Port A configuration */
  39         {                                                       /* conf ppar psor pdir podr pdat */
  40          {0, 1, 0, 0, 0, 0},            /* PA31 FCC1_TXENB  SLAVE */
  41          {0, 1, 0, 1, 0, 0},            /* PA30 FCC1_TXCLAV SLAVE */
  42          {0, 1, 0, 1, 0, 0},            /* PA29 FCC1_TXSOC */
  43          {0, 1, 0, 0, 0, 0},            /* PA28 FCC1_RXENB  SLAVE */
  44          {0, 1, 0, 0, 0, 0},            /* PA27 FCC1_RXSOC */
  45          {0, 1, 0, 1, 0, 0},            /* PA26 FCC1_RXCLAV SLAVE */
  46          {0, 1, 0, 1, 0, 1},            /* PA25 FCC1_TXD0 */
  47          {0, 1, 0, 1, 0, 1},            /* PA24 FCC1_TXD1 */
  48          {0, 1, 0, 1, 0, 1},            /* PA23 FCC1_TXD2 */
  49          {0, 1, 0, 1, 0, 1},            /* PA22 FCC1_TXD3 */
  50          {0, 1, 0, 1, 0, 1},            /* PA21 FCC1_TXD4 */
  51          {0, 1, 0, 1, 0, 1},            /* PA20 FCC1_TXD5 */
  52          {0, 1, 0, 1, 0, 1},            /* PA19 FCC1_TXD6 */
  53          {0, 1, 0, 1, 0, 1},            /* PA18 FCC1_TXD7 */
  54          {0, 1, 0, 0, 0, 0},            /* PA17 FCC1_RXD7 */
  55          {0, 1, 0, 0, 0, 0},            /* PA16 FCC1_RXD6 */
  56          {0, 1, 0, 0, 0, 0},            /* PA15 FCC1_RXD5 */
  57          {0, 1, 0, 0, 0, 0},            /* PA14 FCC1_RXD4 */
  58          {0, 1, 0, 0, 0, 0},            /* PA13 FCC1_RXD3 */
  59          {0, 1, 0, 0, 0, 0},            /* PA12 FCC1_RXD2 */
  60          {0, 1, 0, 0, 0, 0},            /* PA11 FCC1_RXD1 */
  61          {0, 1, 0, 0, 0, 0},            /* PA10 FCC1_RXD0 */
  62          {0, 1, 1, 1, 0, 1},            /* PA9  TDMA1_L1TXD */
  63          {0, 1, 1, 0, 0, 0},            /* PA8  TDMA1_L1RXD */
  64          {0, 0, 0, 0, 0, 0},            /* PA7  CONFIG0 */
  65          {0, 1, 1, 0, 0, 1},            /* PA6  TDMA1_L1RSYNC */
  66          {0, 0, 0, 1, 0, 0},            /* PA5  FCC2:RxAddr[2] */
  67          {0, 0, 0, 1, 0, 0},            /* PA4  FCC2:RxAddr[1] */
  68          {0, 0, 0, 1, 0, 0},            /* PA3  FCC2:RxAddr[0] */
  69          {0, 0, 0, 1, 0, 0},            /* PA2  FCC2:TxAddr[0] */
  70          {0, 0, 0, 1, 0, 0},            /* PA1  FCC2:TxAddr[1] */
  71          {0, 0, 0, 1, 0, 0}                     /* PA0  FCC2:TxAddr[2] */
  72          },
  73         /* Port B configuration */
  74         {                                                       /* conf ppar psor pdir podr pdat */
  75          {0, 0, 0, 1, 0, 0},            /* PB31 FCC2_RXSOC */
  76          {0, 0, 0, 1, 0, 0},            /* PB30 FCC2_TXSOC */
  77          {0, 0, 0, 1, 0, 0},            /* PB29 FCC2_RXCLAV */
  78          {0, 0, 0, 0, 0, 0},            /* PB28 CONFIG2 */
  79          {0, 1, 1, 0, 0, 1},            /* PB27 FCC2_TXD0 */
  80          {0, 1, 1, 0, 0, 0},            /* PB26 FCC2_TXD1 */
  81          {0, 0, 0, 1, 0, 0},            /* PB25 FCC2_TXD4 */
  82          {0, 1, 1, 0, 0, 1},            /* PB24 FCC2_TXD5 */
  83          {0, 0, 0, 1, 0, 0},            /* PB23 FCC2_TXD6 */
  84          {0, 1, 0, 1, 0, 1},            /* PB22 FCC2_TXD7 */
  85          {0, 1, 0, 0, 0, 0},            /* PB21 FCC2_RXD7 */
  86          {0, 1, 0, 0, 0, 0},            /* PB20 FCC2_RXD6 */
  87          {0, 1, 0, 0, 0, 0},            /* PB19 FCC2_RXD5 */
  88          {0, 0, 0, 1, 0, 0},            /* PB18 FCC2_RXD4 */
  89          {1, 1, 0, 0, 0, 0},            /* PB17 FCC3_RX_DV */
  90          {1, 1, 0, 0, 0, 0},            /* PB16 FCC3_RX_ER */
  91          {1, 1, 0, 1, 0, 0},            /* PB15 FCC3_TX_ER */
  92          {1, 1, 0, 1, 0, 0},            /* PB14 FCC3_TX_EN */
  93          {1, 1, 0, 0, 0, 0},            /* PB13 FCC3_COL */
  94          {1, 1, 0, 0, 0, 0},            /* PB12 FCC3_CRS */
  95          {1, 1, 0, 0, 0, 0},            /* PB11 FCC3_RXD3 */
  96          {1, 1, 0, 0, 0, 0},            /* PB10 FCC3_RXD2 */
  97          {1, 1, 0, 0, 0, 0},            /* PB9  FCC3_RXD1 */
  98          {1, 1, 0, 0, 0, 0},            /* PB8  FCC3_RXD0 */
  99          {1, 1, 0, 1, 0, 1},            /* PB7  FCC3_TXD0 */
 100          {1, 1, 0, 1, 0, 1},            /* PB6  FCC3_TXD1 */
 101          {1, 1, 0, 1, 0, 1},            /* PB5  FCC3_TXD2 */
 102          {1, 1, 0, 1, 0, 1},            /* PB4  FCC3_TXD3 */
 103          {0, 0, 0, 0, 0, 0},            /* PB3  */
 104          {0, 0, 0, 0, 0, 0},            /* PB2  */
 105          {0, 0, 0, 0, 0, 0},            /* PB1  */
 106          {0, 0, 0, 0, 0, 0},            /* PB0  */
 107          },
 108         /* Port C configuration */
 109         {                                                       /* conf ppar psor pdir podr pdat */
 110          {0, 1, 0, 0, 0, 1},            /* PC31 CLK1 */
 111          {0, 0, 0, 1, 0, 0},            /* PC30 U1MASTER_N */
 112          {0, 1, 0, 0, 0, 1},            /* PC29 CLK3 */
 113          {0, 0, 0, 1, 0, 1},            /* PC28 -MT90220_RST */
 114          {0, 1, 0, 0, 0, 1},            /* PC27 CLK5 */
 115          {0, 0, 0, 1, 0, 1},            /* PC26 -QUADFALC_RST */
 116          {0, 1, 1, 1, 0, 1},            /* PC25 BRG4 */
 117          {1, 0, 0, 1, 0, 0},            /* PC24 MDIO */
 118          {1, 0, 0, 1, 0, 0},            /* PC23 MDC */
 119          {0, 1, 0, 0, 0, 1},            /* PC22 CLK10 */
 120          {0, 0, 0, 1, 0, 0},            /* PC21  */
 121          {0, 1, 0, 0, 0, 1},            /* PC20 CLK12 */
 122          {0, 1, 0, 0, 0, 1},            /* PC19 CLK13 */
 123          {1, 1, 0, 0, 0, 1},            /* PC18 CLK14 */
 124          {0, 1, 0, 0, 0, 0},            /* PC17 CLK15 */
 125          {1, 1, 0, 0, 0, 1},            /* PC16 CLK16 */
 126          {0, 1, 1, 0, 0, 0},            /* PC15 FCC1_TXADDR0 SLAVE */
 127          {0, 1, 1, 0, 0, 0},            /* PC14 FCC1_RXADDR0 SLAVE */
 128          {0, 1, 1, 0, 0, 0},            /* PC13 FCC1_TXADDR1 SLAVE */
 129          {0, 1, 1, 0, 0, 0},            /* PC12 FCC1_RXADDR1 SLAVE */
 130          {0, 0, 0, 1, 0, 0},            /* PC11 FCC2_RXD2 */
 131          {0, 0, 0, 1, 0, 0},            /* PC10 FCC2_RXD3 */
 132          {0, 0, 0, 1, 0, 1},            /* PC9  LTMODE */
 133          {0, 0, 0, 1, 0, 1},            /* PC8  SELSYNC */
 134          {0, 1, 1, 0, 0, 0},            /* PC7  FCC1_TXADDR2 SLAVE  */
 135          {0, 1, 1, 0, 0, 0},            /* PC6  FCC1_RXADDR2 SLAVE */
 136          {0, 0, 0, 1, 0, 0},            /* PC5  FCC2_TXCLAV MASTER */
 137          {0, 0, 0, 1, 0, 0},            /* PC4  FCC2_RXENB MASTER */
 138          {0, 0, 0, 1, 0, 0},            /* PC3  FCC2_TXD2 */
 139          {0, 0, 0, 1, 0, 0},            /* PC2  FCC2_TXD3 */
 140          {0, 0, 0, 0, 0, 1},            /* PC1  PTMC -PTEENB */
 141          {0, 0, 0, 1, 0, 1},            /* PC0  COMCLK_N */
 142          },
 143         /* Port D configuration */
 144         {                                                       /* conf ppar psor pdir podr pdat */
 145          {0, 0, 0, 1, 0, 1},            /* PD31 -CAM_RST */
 146          {0, 0, 0, 1, 0, 0},            /* PD30 FCC2_TXENB */
 147          {0, 1, 1, 0, 0, 0},            /* PD29 FCC1_RXADDR3 SLAVE */
 148          {0, 1, 1, 0, 0, 1},            /* PD28 TDMC1_L1TXD */
 149          {0, 1, 1, 0, 0, 0},            /* PD27 TDMC1_L1RXD */
 150          {0, 1, 1, 0, 0, 1},            /* PD26 TDMC1_L1RSYNC */
 151          {0, 0, 0, 1, 0, 1},            /* PD25 LED0 -OFF */
 152          {0, 0, 0, 1, 0, 1},            /* PD24 LED5 -OFF */
 153          {1, 0, 0, 1, 0, 1},            /* PD23 -LXT971_RST */
 154          {0, 1, 1, 0, 0, 1},            /* PD22 TDMA2_L1TXD */
 155          {0, 1, 1, 0, 0, 0},            /* PD21 TDMA2_L1RXD */
 156          {0, 1, 1, 0, 0, 1},            /* PD20 TDMA2_L1RSYNC */
 157          {0, 0, 0, 1, 0, 0},            /* PD19 FCC2_TXADDR3 */
 158          {0, 0, 0, 1, 0, 0},            /* PD18 FCC2_RXADDR3 */
 159          {0, 1, 0, 1, 0, 0},            /* PD17 BRG2 */
 160          {0, 0, 0, 1, 0, 0},            /* PD16  */
 161          {0, 0, 0, 1, 0, 0},            /* PD15 PT2TO1 */
 162          {0, 0, 0, 1, 0, 1},            /* PD14 PT4TO3 */
 163          {0, 0, 0, 1, 0, 1},            /* PD13 -SWMODE */
 164          {0, 0, 0, 1, 0, 1},            /* PD12 -PTMODE */
 165          {0, 0, 0, 1, 0, 0},            /* PD11 FCC2_RXD0 */
 166          {0, 0, 0, 1, 0, 0},            /* PD10 FCC2_RXD1 */
 167          {1, 1, 0, 1, 0, 1},            /* PD9  SMC1_SMTXD */
 168          {1, 1, 0, 0, 0, 1},            /* PD8  SMC1_SMRXD */
 169          {0, 1, 1, 0, 0, 0},            /* PD7  FCC1_TXADDR3 SLAVE */
 170          {0, 0, 0, 1, 0, 0},            /* PD6  IMAMODE */
 171          {0, 0, 0, 0, 0, 0},            /* PD5  CONFIG2 */
 172          {0, 1, 0, 1, 0, 0},            /* PD4  BRG8 */
 173          {0, 0, 0, 0, 0, 0},            /* PD3  */
 174          {0, 0, 0, 0, 0, 0},            /* PD2  */
 175          {0, 0, 0, 0, 0, 0},            /* PD1  */
 176          {0, 0, 0, 0, 0, 0},            /* PD0  */
 177          }
 178 };
 179
 180 phys_size_t initdram (int board_type)
 181 {
 182         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 183         volatile memctl8260_t *memctl = &immap->im_memctl;
 184         volatile uchar *base;
 185         ulong maxsize;
 186         int i;
 187
 188         memctl->memc_psrt = CONFIG_SYS_PSRT;
 189         memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 190
 191 #ifndef CONFIG_SYS_RAMBOOT
 192         immap->im_siu_conf.sc_ppc_acr = 0x00000026;
 193         immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
 194         immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
 195         immap->im_siu_conf.sc_lcl_acr = 0x00000000;
 196         immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
 197         immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
 198         immap->im_siu_conf.sc_tescr1 = 0x00004000;
 199         immap->im_siu_conf.sc_ltescr1 = 0x00004000;
 200
 201         /* Init Main SDRAM */
 202 #define OP_VALUE   0x404A241A
 203 #define OP_VALUE_M (OP_VALUE & 0x87FFFFFF);
 204         base = (uchar *) CONFIG_SYS_SDRAM_BASE;
 205         memctl->memc_psdmr = 0x28000000 | OP_VALUE_M;
 206         *base = 0xFF;
 207         memctl->memc_psdmr = 0x08000000 | OP_VALUE_M;
 208         for (i = 0; i < 8; i++)
 209                 *base = 0xFF;
 210         memctl->memc_psdmr = 0x18000000 | OP_VALUE_M;
 211         *(base + 0x110) = 0xFF;
 212         memctl->memc_psdmr = OP_VALUE;
 213         memctl->memc_lsdmr = 0x4086A522;
 214         *base = 0xFF;
 215
 216         /* We must be able to test a location outsize the maximum legal size
 217          * to find out THAT we are outside; but this address still has to be
 218          * mapped by the controller. That means, that the initial mapping has
 219          * to be (at least) twice as large as the maximum expected size.
 220          */
 221         maxsize = (1 + (~memctl->memc_or1 | 0x7fff)) / 2;
 222
 223         maxsize = get_ram_size((long *)base, maxsize);
 224
 225         memctl->memc_or1 |= ~(maxsize - 1);
 226
 227         if (maxsize != hwc_main_sdram_size ())
 228                 printf ("Oops: memory test has not found all memory!\n");
 229 #endif
 230
 231         icache_enable ();
 232         /* return total ram size of SDRAM */
 233         return (maxsize);
 234 }
 235
 236 int checkboard (void)
 237 {
 238         char string[32];
 239
 240         hwc_manufact_date (string);
 241
 242         printf ("Board: Interphase 4539 (#%d %s)\n",
 243                 hwc_serial_number (),
 244                 string);
 245
 246 #ifdef DEBUG
 247         printf ("Manufacturing date: %s\n", string);
 248         printf ("Serial number     : %d\n", hwc_serial_number ());
 249         printf ("FLASH size        : %d MB\n", hwc_flash_size () >> 20);
 250         printf ("Main SDRAM size   : %d MB\n", hwc_main_sdram_size () >> 20);
 251         printf ("Local SDRAM size  : %d MB\n", hwc_local_sdram_size () >> 20);
 252         hwc_mac_address (string);
 253         printf ("MAC address       : %s\n", string);
 254 #endif
 255
 256         return 0;
 257 }
 258
 259 int misc_init_r (void)
 260 {
 261         char *s, str[32];
 262         int num;
 263
 264         if ((s = getenv ("serial#")) == NULL &&
 265                 (num = hwc_serial_number ()) != -1) {
 266                 sprintf (str, "%06d", num);
 267                 setenv ("serial#", str);
 268         }
 269         if ((s = getenv ("ethaddr")) == NULL && hwc_mac_address (str) == 0) {
 270                 setenv ("ethaddr", str);
 271         }
 272         return (0);
 273 }
 274
 275 /***************************************************************
 276  * We take some basic Hardware Configuration Parameter from the
 277  * Serial EEPROM conected to the PSpan bridge. We keep it as
 278  * simple as possible.
 279  */
 280 int hwc_flash_size (void)
 281 {
 282         uchar byte;
 283
 284         if (!seeprom_read (0x40, &byte, sizeof (byte))) {
 285                 switch ((byte >> 2) & 0x3) {
 286                 case 0x1:
 287                         return 0x0400000;
 288                         break;
 289                 case 0x2:
 290                         return 0x0800000;
 291                         break;
 292                 case 0x3:
 293                         return 0x1000000;
 294                 default:
 295                         return 0x0100000;
 296                 }
 297         }
 298         return -1;
 299 }
 300 int hwc_local_sdram_size (void)
 301 {
 302         uchar byte;
 303
 304         if (!seeprom_read (0x40, &byte, sizeof (byte))) {
 305                 switch ((byte & 0x03)) {
 306                 case 0x1:
 307                         return 0x0800000;
 308                 case 0x2:
 309                         return 0x1000000;
 310                 default:
 311                         return 0;                       /* not present */
 312                 }
 313         }
 314         return -1;
 315 }
 316 int hwc_main_sdram_size (void)
 317 {
 318         uchar byte;
 319
 320         if (!seeprom_read (0x41, &byte, sizeof (byte))) {
 321                 return 0x1000000 << ((byte >> 5) & 0x7);
 322         }
 323         return -1;
 324 }
 325 int hwc_serial_number (void)
 326 {
 327         int sn = -1;
 328
 329         if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) {
 330                 sn = cpu_to_le32 (sn);
 331         }
 332         return sn;
 333 }
 334 int hwc_mac_address (char *str)
 335 {
 336         char mac[6];
 337
 338         if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) {
 339                 sprintf (str, "%02x:%02x:%02x:%02x:%02x:%02x\n",
 340                                  mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 341         } else {
 342                 strcpy (str, "ERROR");
 343                 return -1;
 344         }
 345         return 0;
 346 }
 347 int hwc_manufact_date (char *str)
 348 {
 349         uchar byte;
 350         int value;
 351
 352         if (seeprom_read (0x92, &byte, sizeof (byte)))
 353                 goto out;
 354         value = byte;
 355         if (seeprom_read (0x93, &byte, sizeof (byte)))
 356                 goto out;
 357         value += byte << 8;
 358         sprintf (str, "%02d/%02d/%04d",
 359                          value & 0x1F, (value >> 5) & 0xF,
 360                          1980 + ((value >> 9) & 0x1FF));
 361         return 0;
 362
 363   out:
 364         strcpy (str, "ERROR");
 365         return -1;
 366 }
 367
 368 #define PSPAN_ADDR      0xF0020000
 369 #define EEPROM_REG      0x408
 370 #define EEPROM_READ_CMD 0xA000
 371 #define PSPAN_WRITE(a,v) \
 372     *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio()
 373 #define PSPAN_READ(a) \
 374     *((volatile unsigned long *)(PSPAN_ADDR+(a)))
 375
 376 int seeprom_read (int addr, uchar * data, int size)
 377 {
 378         ulong val, cmd;
 379         int i;
 380
 381         for (i = 0; i < size; i++) {
 382
 383                 cmd = EEPROM_READ_CMD;
 384                 cmd |= ((addr + i) << 24) & 0xff000000;
 385
 386                 /* Wait for ACT to authorize write */
 387                 while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
 388                         eieio ();
 389
 390                 /* Write command */
 391                 PSPAN_WRITE (EEPROM_REG, cmd);
 392
 393                 /* Wait for data to be valid */
 394                 while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
 395                         eieio ();
 396                 /* Do it twice, first read might be erratic */
 397                 while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
 398                         eieio ();
 399
 400                 /* Read error */
 401                 if (val & 0x00000040) {
 402                         return -1;
 403                 } else {
 404                         data[i] = (val >> 16) & 0xff;
 405                 }
 406         }
 407         return 0;
 408 }