board/jupiter/jupiter.c

   1 /*
   2  * (C) Copyright 2007
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <mpc5xxx.h>
  13 #include <pci.h>
  14 #include <asm/processor.h>
  15 #include <libfdt.h>
  16
  17 #define SDRAM_DDR       0
  18 #if 1
  19 /* Settings Icecube */
  20 #define SDRAM_MODE      0x00CD0000
  21 #define SDRAM_CONTROL   0x504F0000
  22 #define SDRAM_CONFIG1   0xD2322800
  23 #define SDRAM_CONFIG2   0x8AD70000
  24 #else
  25 /*Settings Jupiter UB 1.0.0 */
  26 #define SDRAM_MODE      0x008D0000
  27 #define SDRAM_CONTROL   0xD04F0000
  28 #define SDRAM_CONFIG1   0xf7277f00
  29 #define SDRAM_CONFIG2   0x88b70004
  30 #endif
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #ifndef CONFIG_SYS_RAMBOOT
  35 static void sdram_start (int hi_addr)
  36 {
  37         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  38
  39         /* unlock mode register */
  40         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  41         __asm__ volatile ("sync");
  42
  43         /* precharge all banks */
  44         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  45         __asm__ volatile ("sync");
  46
  47 #if SDRAM_DDR
  48         /* set mode register: extended mode */
  49         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  50         __asm__ volatile ("sync");
  51
  52         /* set mode register: reset DLL */
  53         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  54         __asm__ volatile ("sync");
  55 #endif
  56
  57         /* precharge all banks */
  58         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  59         __asm__ volatile ("sync");
  60
  61         /* auto refresh */
  62         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
  63         __asm__ volatile ("sync");
  64
  65         /* set mode register */
  66         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  67         __asm__ volatile ("sync");
  68
  69         /* normal operation */
  70         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  71         __asm__ volatile ("sync");
  72 }
  73 #endif
  74
  75 /*
  76  * ATTENTION: Although partially referenced initdram does NOT make real use
  77  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  78  *            is something else than 0x00000000.
  79  */
  80
  81 int initdram(void)
  82 {
  83         ulong dramsize = 0;
  84         ulong dramsize2 = 0;
  85         uint svr, pvr;
  86
  87 #ifndef CONFIG_SYS_RAMBOOT
  88         ulong test1, test2;
  89
  90         /* setup SDRAM chip selects */
  91         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
  92         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
  93         __asm__ volatile ("sync");
  94
  95         /* setup config registers */
  96         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
  97         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
  98         __asm__ volatile ("sync");
  99
 100 #if SDRAM_DDR
 101         /* set tap delay */
 102         *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 103         __asm__ volatile ("sync");
 104 #endif
 105
 106         /* find RAM size using SDRAM CS0 only */
 107         sdram_start(0);
 108         test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 109         sdram_start(1);
 110         test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 111         if (test1 > test2) {
 112                 sdram_start(0);
 113                 dramsize = test1;
 114         } else {
 115                 dramsize = test2;
 116         }
 117
 118         /* memory smaller than 1MB is impossible */
 119         if (dramsize < (1 << 20)) {
 120                 dramsize = 0;
 121         }
 122
 123         /* set SDRAM CS0 size according to the amount of RAM found */
 124         if (dramsize > 0) {
 125                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
 126         } else {
 127                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 128         }
 129
 130         /* let SDRAM CS1 start right after CS0 */
 131         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
 132
 133         /* find RAM size using SDRAM CS1 only */
 134         if (!dramsize)
 135                 sdram_start(0);
 136         test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 137         if (!dramsize) {
 138                 sdram_start(1);
 139                 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 140         }
 141         if (test1 > test2) {
 142                 sdram_start(0);
 143                 dramsize2 = test1;
 144         } else {
 145                 dramsize2 = test2;
 146         }
 147
 148         /* memory smaller than 1MB is impossible */
 149         if (dramsize2 < (1 << 20)) {
 150                 dramsize2 = 0;
 151         }
 152
 153         /* set SDRAM CS1 size according to the amount of RAM found */
 154         if (dramsize2 > 0) {
 155                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 156                         | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 157         } else {
 158                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 159         }
 160
 161 #else /* CONFIG_SYS_RAMBOOT */
 162
 163         /* retrieve size of memory connected to SDRAM CS0 */
 164         dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 165         if (dramsize >= 0x13) {
 166                 dramsize = (1 << (dramsize - 0x13)) << 20;
 167         } else {
 168                 dramsize = 0;
 169         }
 170
 171         /* retrieve size of memory connected to SDRAM CS1 */
 172         dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 173         if (dramsize2 >= 0x13) {
 174                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 175         } else {
 176                 dramsize2 = 0;
 177         }
 178
 179 #endif /* CONFIG_SYS_RAMBOOT */
 180
 181         /*
 182          * On MPC5200B we need to set the special configuration delay in the
 183          * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
 184          * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
 185          *
 186          * "The SDelay should be written to a value of 0x00000004. It is
 187          * required to account for changes caused by normal wafer processing
 188          * parameters."
 189          */
 190         svr = get_svr();
 191         pvr = get_pvr();
 192         if ((SVR_MJREV(svr) >= 2) &&
 193             (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
 194
 195                 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
 196                 __asm__ volatile ("sync");
 197         }
 198
 199         gd->ram_size = dramsize + dramsize2;
 200
 201         return 0;
 202 }
 203
 204 int checkboard (void)
 205 {
 206         puts ("Board: Sauter (Jupiter)\n");
 207         return 0;
 208 }
 209
 210 void flash_preinit(void)
 211 {
 212         /*
 213          * Now, when we are in RAM, enable flash write
 214          * access for detection process.
 215          * Note that CS_BOOT cannot be cleared when
 216          * executing in flash.
 217          */
 218         *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 219 }
 220
 221 int board_early_init_r (void)
 222 {
 223         flash_preinit ();
 224         return 0;
 225 }
 226
 227 void flash_afterinit(ulong size)
 228 {
 229         if (size == 0x1000000) { /* adjust mapping */
 230                 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
 231                         START_REG(CONFIG_SYS_BOOTCS_START | size);
 232                 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 233                         STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
 234         }
 235         *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
 236         *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
 237 }
 238
 239 int update_flash_size (int flash_size)
 240 {
 241         flash_afterinit (flash_size);
 242         return 0;
 243 }
 244
 245 int board_early_init_f (void)
 246 {
 247         *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 248         return 0;
 249 }
 250
 251 #ifdef  CONFIG_PCI
 252 static struct pci_controller hose;
 253
 254 extern void pci_mpc5xxx_init(struct pci_controller *);
 255
 256 void pci_init_board(void)
 257 {
 258         pci_mpc5xxx_init(&hose);
 259 }
 260 #endif
 261
 262 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 263
 264 void init_ide_reset (void)
 265 {
 266         debug ("init_ide_reset\n");
 267
 268         /* Configure PSC1_4 as GPIO output for ATA reset */
 269         *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
 270         *(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
 271         /* Deassert reset */
 272         *(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC1_4;
 273 }
 274
 275 void ide_set_reset (int idereset)
 276 {
 277         debug ("ide_reset(%d)\n", idereset);
 278
 279         if (idereset) {
 280                 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
 281                 /* Make a delay. MPC5200 spec says 25 usec min */
 282                 udelay(500000);
 283         } else {
 284                 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
 285         }
 286 }
 287 #endif
 288
 289 #ifdef CONFIG_OF_BOARD_SETUP
 290 int ft_board_setup(void *blob, bd_t *bd)
 291 {
 292         ft_cpu_setup(blob, bd);
 293
 294         return 0;
 295 }
 296 #endif /* CONFIG_OF_BOARD_SETUP */