board/keymile/km82xx/km82xx.c

   1 /*
   2  * (C) Copyright 2007 - 2008
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <mpc8260.h>
  10 #include <ioports.h>
  11 #include <malloc.h>
  12 #include <asm/io.h>
  13
  14 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
  15 #include <libfdt.h>
  16 #endif
  17
  18 #include <i2c.h>
  19 #include "../common/common.h"
  20
  21 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
  22
  23 /*
  24  * I/O Port configuration table
  25  *
  26  * if conf is 1, then that port pin will be configured at boot time
  27  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  28  */
  29 const iop_conf_t iop_conf_tab[4][32] = {
  30
  31         /* Port A */
  32         {       /*            conf      ppar psor pdir podr pdat */
  33                 { 0,             0,   0,   0,   0,   0 }, /* PA31            */
  34                 { 0,             0,   0,   0,   0,   0 }, /* PA30            */
  35                 { 0,             0,   0,   0,   0,   0 }, /* PA29            */
  36                 { 0,             0,   0,   0,   0,   0 }, /* PA28            */
  37                 { 0,             0,   0,   0,   0,   0 }, /* PA27            */
  38                 { 0,             0,   0,   0,   0,   0 }, /* PA26            */
  39                 { 0,             0,   0,   0,   0,   0 }, /* PA25            */
  40                 { 0,             0,   0,   0,   0,   0 }, /* PA24            */
  41                 { 0,             0,   0,   0,   0,   0 }, /* PA23            */
  42                 { 0,             0,   0,   0,   0,   0 }, /* PA22            */
  43                 { 0,             0,   0,   0,   0,   0 }, /* PA21            */
  44                 { 0,             0,   0,   0,   0,   0 }, /* PA20            */
  45                 { 0,             0,   0,   0,   0,   0 }, /* PA19            */
  46                 { 0,             0,   0,   0,   0,   0 }, /* PA18            */
  47                 { 0,             0,   0,   0,   0,   0 }, /* PA17            */
  48                 { 0,             0,   0,   0,   0,   0 }, /* PA16            */
  49                 { 0,             0,   0,   0,   0,   0 }, /* PA15            */
  50                 { 0,             0,   0,   0,   0,   0 }, /* PA14            */
  51                 { 0,             0,   0,   0,   0,   0 }, /* PA13            */
  52                 { 0,             0,   0,   0,   0,   0 }, /* PA12            */
  53                 { 0,             0,   0,   0,   0,   0 }, /* PA11            */
  54                 { 0,             0,   0,   0,   0,   0 }, /* PA10            */
  55                 { 1,             1,   0,   1,   0,   0 }, /* PA9 SMC2 TxD    */
  56                 { 1,             1,   0,   0,   0,   0 }, /* PA8 SMC2 RxD    */
  57                 { 0,             0,   0,   0,   0,   0 }, /* PA7             */
  58                 { 0,             0,   0,   0,   0,   0 }, /* PA6             */
  59                 { 0,             0,   0,   0,   0,   0 }, /* PA5             */
  60                 { 0,             0,   0,   0,   0,   0 }, /* PA4             */
  61                 { 0,             0,   0,   0,   0,   0 }, /* PA3             */
  62                 { 0,             0,   0,   0,   0,   0 }, /* PA2             */
  63                 { 0,             0,   0,   0,   0,   0 }, /* PA1             */
  64                 { 0,             0,   0,   0,   0,   0 }  /* PA0             */
  65         },
  66
  67         /* Port B */
  68         {       /*            conf      ppar psor pdir podr pdat */
  69                 { 0,             0,   0,   0,   0,   0 }, /* PB31            */
  70                 { 0,             0,   0,   0,   0,   0 }, /* PB30            */
  71                 { 0,             0,   0,   0,   0,   0 }, /* PB29            */
  72                 { 0,             0,   0,   0,   0,   0 }, /* PB28            */
  73                 { 0,             0,   0,   0,   0,   0 }, /* PB27            */
  74                 { 0,             0,   0,   0,   0,   0 }, /* PB26            */
  75                 { 0,             0,   0,   0,   0,   0 }, /* PB25            */
  76                 { 0,             0,   0,   0,   0,   0 }, /* PB24            */
  77                 { 0,             0,   0,   0,   0,   0 }, /* PB23            */
  78                 { 0,             0,   0,   0,   0,   0 }, /* PB22            */
  79                 { 0,             0,   0,   0,   0,   0 }, /* PB21            */
  80                 { 0,             0,   0,   0,   0,   0 }, /* PB20            */
  81                 { 0,             0,   0,   0,   0,   0 }, /* PB19            */
  82                 { 0,             0,   0,   0,   0,   0 }, /* PB18            */
  83                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  84                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  85                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  86                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  87                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  88                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  89                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  90                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  91                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  92                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  93                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  94                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  95                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  96                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  97                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  98                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  99                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 100                 { 0,             0,   0,   0,   0,   0 }  /* non-existent    */
 101         },
 102
 103         /* Port C */
 104         {       /*            conf      ppar psor pdir podr pdat */
 105                 { 0,             0,   0,   0,   0,   0 }, /* PC31            */
 106                 { 0,             0,   0,   0,   0,   0 }, /* PC30            */
 107                 { 0,             0,   0,   0,   0,   0 }, /* PC29            */
 108                 { 0,             0,   0,   0,   0,   0 }, /* PC28            */
 109                 { 0,             0,   0,   0,   0,   0 }, /* PC27            */
 110                 { 0,             0,   0,   0,   0,   0 }, /* PC26            */
 111                 { 1,             1,   0,   0,   0,   0 }, /* PC25 RxClk      */
 112                 { 1,             1,   0,   0,   0,   0 }, /* PC24 TxClk      */
 113                 { 0,             0,   0,   0,   0,   0 }, /* PC23            */
 114                 { 0,             0,   0,   0,   0,   0 }, /* PC22            */
 115                 { 0,             0,   0,   0,   0,   0 }, /* PC21            */
 116                 { 0,             0,   0,   0,   0,   0 }, /* PC20            */
 117                 { 0,             0,   0,   0,   0,   0 }, /* PC19            */
 118                 { 0,             0,   0,   0,   0,   0 }, /* PC18            */
 119                 { 0,             0,   0,   0,   0,   0 }, /* PC17            */
 120                 { 0,             0,   0,   0,   0,   0 }, /* PC16            */
 121                 { 0,             0,   0,   0,   0,   0 }, /* PC15            */
 122                 { 0,             0,   0,   0,   0,   0 }, /* PC14            */
 123                 { 0,             0,   0,   0,   0,   0 }, /* PC13            */
 124                 { 0,             0,   0,   0,   0,   0 }, /* PC12            */
 125                 { 0,             0,   0,   0,   0,   0 }, /* PC11            */
 126                 { 0,             0,   0,   0,   0,   0 }, /* PC10            */
 127                 { 1,             1,   0,   0,   0,   0 }, /* PC9  SCC4: CTS  */
 128                 { 1,             1,   0,   0,   0,   0 }, /* PC8  SCC4: CD   */
 129                 { 0,             0,   0,   0,   0,   0 }, /* PC7             */
 130                 { 0,             0,   0,   0,   0,   0 }, /* PC6             */
 131                 { 0,             0,   0,   0,   0,   0 }, /* PC5             */
 132                 { 0,             0,   0,   0,   0,   0 }, /* PC4             */
 133                 { 0,             0,   0,   0,   0,   0 }, /* PC3             */
 134                 { 0,             0,   0,   0,   0,   0 }, /* PC2             */
 135                 { 0,             0,   0,   0,   0,   0 }, /* PC1             */
 136                 { 0,             0,   0,   0,   0,   0 }, /* PC0             */
 137         },
 138
 139         /* Port D */
 140         {       /*            conf      ppar psor pdir podr pdat */
 141                 { 0,             0,   0,   0,   0,   0 }, /* PD31            */
 142                 { 0,             0,   0,   0,   0,   0 }, /* PD30            */
 143                 { 0,             0,   0,   0,   0,   0 }, /* PD29            */
 144                 { 0,             0,   0,   0,   0,   0 }, /* PD28            */
 145                 { 0,             0,   0,   0,   0,   0 }, /* PD27            */
 146                 { 0,             0,   0,   0,   0,   0 }, /* PD26            */
 147                 { 0,             0,   0,   0,   0,   0 }, /* PD25            */
 148                 { 0,             0,   0,   0,   0,   0 }, /* PD24            */
 149                 { 0,             0,   0,   0,   0,   0 }, /* PD23            */
 150                 { 1,             1,   0,   0,   0,   0 }, /* PD22 SCC4: RXD  */
 151                 { 1,             1,   0,   1,   0,   0 }, /* PD21 SCC4: TXD  */
 152                 { 1,             1,   0,   1,   0,   0 }, /* PD20 SCC4: RTS  */
 153                 { 0,             0,   0,   0,   0,   0 }, /* PD19            */
 154                 { 0,             0,   0,   0,   0,   0 }, /* PD18            */
 155                 { 0,             0,   0,   0,   0,   0 }, /* PD17            */
 156                 { 0,             0,   0,   0,   0,   0 }, /* PD16            */
 157 #if defined(CONFIG_HARD_I2C)
 158                 { 1,             1,   1,   0,   1,   0 }, /* PD15 I2C SDA    */
 159                 { 1,             1,   1,   0,   1,   0 }, /* PD14 I2C SCL    */
 160 #else
 161                 { 1,             0,   0,   0,   1,   1 }, /* PD15            */
 162                 { 1,             0,   0,   1,   1,   1 }, /* PD14            */
 163 #endif
 164                 { 0,             0,   0,   0,   0,   0 }, /* PD13            */
 165                 { 0,             0,   0,   0,   0,   0 }, /* PD12            */
 166                 { 0,             0,   0,   0,   0,   0 }, /* PD11            */
 167                 { 0,             0,   0,   0,   0,   0 }, /* PD10            */
 168                 { 0,             0,   0,   0,   0,   0 }, /* PD9             */
 169                 { 0,             0,   0,   0,   0,   0 }, /* PD8             */
 170                 { 0,             0,   0,   0,   0,   0 }, /* PD7             */
 171                 { 0,             0,   0,   0,   0,   0 }, /* PD6             */
 172                 { 0,             0,   0,   0,   0,   0 }, /* PD5             */
 173                 { 0,             0,   0,   0,   0,   0 }, /* PD4             */
 174                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 175                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 176                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 177                 { 0,             0,   0,   0,   0,   0 }  /* non-existent    */
 178         }
 179 };
 180
 181 /*
 182  * Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
 183  *
 184  * This routine performs standard 8260 initialization sequence
 185  * and calculates the available memory size. It may be called
 186  * several times to try different SDRAM configurations on both
 187  * 60x and local buses.
 188  */
 189 static long int try_init(memctl8260_t *memctl, ulong sdmr,
 190                                   ulong orx, uchar *base)
 191 {
 192         uchar c = 0xff;
 193         ulong maxsize, size;
 194         int i;
 195
 196         /*
 197          * We must be able to test a location outsize the maximum legal size
 198          * to find out THAT we are outside; but this address still has to be
 199          * mapped by the controller. That means, that the initial mapping has
 200          * to be (at least) twice as large as the maximum expected size.
 201          */
 202         maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
 203
 204         out_be32(&memctl->memc_or1, orx);
 205
 206         /*
 207          * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
 208          *
 209          * "At system reset, initialization software must set up the
 210          *  programmable parameters in the memory controller banks registers
 211          *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
 212          *  system software should execute the following initialization sequence
 213          *  for each SDRAM device.
 214          *
 215          *  1. Issue a PRECHARGE-ALL-BANKS command
 216          *  2. Issue eight CBR REFRESH commands
 217          *  3. Issue a MODE-SET command to initialize the mode register
 218          *
 219          *  The initial commands are executed by setting P/LSDMR[OP] and
 220          *  accessing the SDRAM with a single-byte transaction."
 221          *
 222          * The appropriate BRx/ORx registers have already been set when we
 223          * get here. The SDRAM can be accessed at the address
 224          * CONFIG_SYS_SDRAM_BASE.
 225          */
 226
 227         out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA);
 228         out_8(base, c);
 229
 230         out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR);
 231         for (i = 0; i < 8; i++)
 232                 out_8(base, c);
 233
 234         out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW);
 235         /* setting MR on address lines */
 236         out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c);
 237
 238         out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN);
 239         out_8(base, c);
 240
 241         size = get_ram_size((long *)base, maxsize);
 242         out_be32(&memctl->memc_or1, orx | ~(size - 1));
 243
 244         return size;
 245 }
 246
 247 #ifdef CONFIG_SYS_SDRAM_LIST
 248
 249 /*
 250  * If CONFIG_SYS_SDRAM_LIST is defined, we cycle through all SDRAM
 251  * configurations therein (should be from high to lower) to find the
 252  * one actually matching the current configuration.
 253  * CONFIG_SYS_PSDMR and CONFIG_SYS_OR1 will contain the base values which are
 254  * common among all possible configurations; values in CONFIG_SYS_SDRAM_LIST
 255  * (defined as the initialization value for the array of struct sdram_conf_s)
 256  * will then be ORed with such base values.
 257  */
 258
 259 struct sdram_conf_s {
 260         ulong size;
 261         int or1;
 262         int psdmr;
 263 };
 264
 265 static struct sdram_conf_s sdram_conf[] = CONFIG_SYS_SDRAM_LIST;
 266
 267 static long probe_sdram(memctl8260_t *memctl)
 268 {
 269         int n = 0;
 270         long psize = 0;
 271
 272         for (n = 0; n < ARRAY_SIZE(sdram_conf); psize = 0, n++) {
 273                 psize = try_init(memctl,
 274                         CONFIG_SYS_PSDMR | sdram_conf[n].psdmr,
 275                         CONFIG_SYS_OR1 | sdram_conf[n].or1,
 276                         (uchar *) CONFIG_SYS_SDRAM_BASE);
 277                 debug("Probing %ld bytes returned %ld\n",
 278                         sdram_conf[n].size, psize);
 279                 if (psize == sdram_conf[n].size)
 280                         break;
 281         }
 282         return psize;
 283 }
 284
 285 #else /* CONFIG_SYS_SDRAM_LIST */
 286
 287 static long probe_sdram(memctl8260_t *memctl)
 288 {
 289         return try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
 290                                         (uchar *) CONFIG_SYS_SDRAM_BASE);
 291 }
 292 #endif /* CONFIG_SYS_SDRAM_LIST */
 293
 294
 295 phys_size_t initdram(int board_type)
 296 {
 297         immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 298         memctl8260_t *memctl = &immap->im_memctl;
 299
 300         long psize;
 301
 302         out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT);
 303         out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
 304
 305         /* 60x SDRAM setup:
 306          */
 307         psize = probe_sdram(memctl);
 308
 309         icache_enable();
 310
 311         return psize;
 312 }
 313
 314 int checkboard(void)
 315 {
 316 #if defined(CONFIG_MGCOGE)
 317         puts("Board: Keymile mgcoge");
 318 #else
 319         puts("Board: Keymile mgcoge3ne");
 320 #endif
 321         if (ethernet_present())
 322                 puts(" with PIGGY.");
 323         puts("\n");
 324         return 0;
 325 }
 326
 327 int last_stage_init(void)
 328 {
 329         struct bfticu_iomap *base =
 330                 (struct bfticu_iomap *)CONFIG_SYS_FPGA_BASE;
 331         u8 dip_switch;
 332
 333         dip_switch = in_8(&base->mswitch);
 334         dip_switch &= BFTICU_DIPSWITCH_MASK;
 335         /* dip switch 'full reset' or 'db erase' */
 336         if (dip_switch & 0x1 || dip_switch & 0x2) {
 337                 /* start bootloader */
 338                 puts("DIP:   Enabled\n");
 339                 setenv("actual_bank", "0");
 340         }
 341         set_km_env();
 342         return 0;
 343 }
 344
 345 #ifdef CONFIG_MGCOGE3NE
 346 static void set_pin(int state, unsigned long mask, int port);
 347
 348 /*
 349  * For mgcoge3ne boards, the mgcoge3un control is controlled from
 350  * a GPIO line on the PPC CPU. If bobcatreset is set the line
 351  * will toggle once what forces the mgocge3un part to restart
 352  * immediately.
 353  */
 354 static void handle_mgcoge3un_reset(void)
 355 {
 356         char *bobcatreset = getenv("bobcatreset");
 357         if (bobcatreset) {
 358                 if (strcmp(bobcatreset, "true") == 0) {
 359                         puts("Forcing bobcat reset\n");
 360                         set_pin(0, 0x00000004, 3); /* clear PD29 (reset arm) */
 361                         udelay(1000);
 362                         set_pin(1, 0x00000004, 3);
 363                 } else
 364                         set_pin(1, 0x00000004, 3); /* don't reset arm */
 365         }
 366 }
 367 #endif
 368
 369 int ethernet_present(void)
 370 {
 371         struct km_bec_fpga *base =
 372                 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
 373
 374         return in_8(&base->bprth) & PIGGY_PRESENT;
 375 }
 376
 377 /*
 378  * Early board initalization.
 379  */
 380 int board_early_init_r(void)
 381 {
 382         struct km_bec_fpga *base =
 383                 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
 384
 385         /* setup the UPIOx */
 386         /* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
 387         out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED));
 388         /* SCC4 enable, halfduplex, FCC1 powerdown */
 389         out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA |
 390                 H_OPORTS_FCC1_PW_DWN));
 391
 392 #ifdef CONFIG_MGCOGE3NE
 393         handle_mgcoge3un_reset();
 394 #endif
 395         return 0;
 396 }
 397
 398 int misc_init_r(void)
 399 {
 400         ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
 401         return 0;
 402 }
 403
 404 int hush_init_var(void)
 405 {
 406         ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
 407         return 0;
 408 }
 409
 410 #define SDA_MASK        0x00010000
 411 #define SCL_MASK        0x00020000
 412
 413 static void set_pin(int state, unsigned long mask, int port)
 414 {
 415         ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port);
 416
 417         if (state)
 418                 setbits_be32(&iop->pdat, mask);
 419         else
 420                 clrbits_be32(&iop->pdat, mask);
 421
 422         setbits_be32(&iop->pdir, mask);
 423 }
 424
 425 static int get_pin(unsigned long mask, int port)
 426 {
 427         ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port);
 428
 429         clrbits_be32(&iop->pdir, mask);
 430         return 0 != (in_be32(&iop->pdat) & mask);
 431 }
 432
 433 void set_sda(int state)
 434 {
 435         set_pin(state, SDA_MASK, 3);
 436 }
 437
 438 void set_scl(int state)
 439 {
 440         set_pin(state, SCL_MASK, 3);
 441 }
 442
 443 int get_sda(void)
 444 {
 445         return get_pin(SDA_MASK, 3);
 446 }
 447
 448 int get_scl(void)
 449 {
 450         return get_pin(SCL_MASK, 3);
 451 }
 452
 453 #if defined(CONFIG_HARD_I2C)
 454 static void setports(int gpio)
 455 {
 456         ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
 457
 458         if (gpio) {
 459                 clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
 460                 clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
 461         } else {
 462                 setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
 463                 clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK));
 464                 setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
 465         }
 466 }
 467 #endif
 468 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
 469 int ft_board_setup(void *blob, bd_t *bd)
 470 {
 471         ft_cpu_setup(blob, bd);
 472
 473         return 0;
 474 }
 475 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
 476
 477 #if defined(CONFIG_MGCOGE3NE)
 478 int get_testpin(void)
 479 {
 480         /* Testpin is Port C pin 29 - enable = low */
 481         int testpin = !get_pin(0x00000004, 2);
 482         return testpin;
 483 }
 484 #endif