board/keymile/km82xx/km82xx.c

   1 /*
   2  * (C) Copyright 2007 - 2008
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <mpc8260.h>
  26 #include <ioports.h>
  27 #include <malloc.h>
  28 #include <asm/io.h>
  29
  30 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
  31 #include <libfdt.h>
  32 #endif
  33
  34 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
  35 #include <i2c.h>
  36 #endif
  37
  38 #include "../common/common.h"
  39
  40 /*
  41  * I/O Port configuration table
  42  *
  43  * if conf is 1, then that port pin will be configured at boot time
  44  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  45  */
  46 const iop_conf_t iop_conf_tab[4][32] = {
  47
  48         /* Port A */
  49         {       /*            conf      ppar psor pdir podr pdat */
  50                 { 0,             0,   0,   0,   0,   0 }, /* PA31            */
  51                 { 0,             0,   0,   0,   0,   0 }, /* PA30            */
  52                 { 0,             0,   0,   0,   0,   0 }, /* PA29            */
  53                 { 0,             0,   0,   0,   0,   0 }, /* PA28            */
  54                 { 0,             0,   0,   0,   0,   0 }, /* PA27            */
  55                 { 0,             0,   0,   0,   0,   0 }, /* PA26            */
  56                 { 0,             0,   0,   0,   0,   0 }, /* PA25            */
  57                 { 0,             0,   0,   0,   0,   0 }, /* PA24            */
  58                 { 0,             0,   0,   0,   0,   0 }, /* PA23            */
  59                 { 0,             0,   0,   0,   0,   0 }, /* PA22            */
  60                 { 0,             0,   0,   0,   0,   0 }, /* PA21            */
  61                 { 0,             0,   0,   0,   0,   0 }, /* PA20            */
  62                 { 0,             0,   0,   0,   0,   0 }, /* PA19            */
  63                 { 0,             0,   0,   0,   0,   0 }, /* PA18            */
  64                 { 0,             0,   0,   0,   0,   0 }, /* PA17            */
  65                 { 0,             0,   0,   0,   0,   0 }, /* PA16            */
  66                 { 0,             0,   0,   0,   0,   0 }, /* PA15            */
  67                 { 0,             0,   0,   0,   0,   0 }, /* PA14            */
  68                 { 0,             0,   0,   0,   0,   0 }, /* PA13            */
  69                 { 0,             0,   0,   0,   0,   0 }, /* PA12            */
  70                 { 0,             0,   0,   0,   0,   0 }, /* PA11            */
  71                 { 0,             0,   0,   0,   0,   0 }, /* PA10            */
  72                 { 1,             1,   0,   1,   0,   0 }, /* PA9 SMC2 TxD    */
  73                 { 1,             1,   0,   0,   0,   0 }, /* PA8 SMC2 RxD    */
  74                 { 0,             0,   0,   0,   0,   0 }, /* PA7             */
  75                 { 0,             0,   0,   0,   0,   0 }, /* PA6             */
  76                 { 0,             0,   0,   0,   0,   0 }, /* PA5             */
  77                 { 0,             0,   0,   0,   0,   0 }, /* PA4             */
  78                 { 0,             0,   0,   0,   0,   0 }, /* PA3             */
  79                 { 0,             0,   0,   0,   0,   0 }, /* PA2             */
  80                 { 0,             0,   0,   0,   0,   0 }, /* PA1             */
  81                 { 0,             0,   0,   0,   0,   0 }  /* PA0             */
  82         },
  83
  84         /* Port B */
  85         {       /*            conf      ppar psor pdir podr pdat */
  86                 { 0,             0,   0,   0,   0,   0 }, /* PB31            */
  87                 { 0,             0,   0,   0,   0,   0 }, /* PB30            */
  88                 { 0,             0,   0,   0,   0,   0 }, /* PB29            */
  89                 { 0,             0,   0,   0,   0,   0 }, /* PB28            */
  90                 { 0,             0,   0,   0,   0,   0 }, /* PB27            */
  91                 { 0,             0,   0,   0,   0,   0 }, /* PB26            */
  92                 { 0,             0,   0,   0,   0,   0 }, /* PB25            */
  93                 { 0,             0,   0,   0,   0,   0 }, /* PB24            */
  94                 { 0,             0,   0,   0,   0,   0 }, /* PB23            */
  95                 { 0,             0,   0,   0,   0,   0 }, /* PB22            */
  96                 { 0,             0,   0,   0,   0,   0 }, /* PB21            */
  97                 { 0,             0,   0,   0,   0,   0 }, /* PB20            */
  98                 { 0,             0,   0,   0,   0,   0 }, /* PB19            */
  99                 { 0,             0,   0,   0,   0,   0 }, /* PB18            */
 100                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 101                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 102                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 103                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 104                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 105                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 106                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 107                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 108                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 109                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 110                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 111                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 112                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 113                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 114                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 115                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 116                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 117                 { 0,             0,   0,   0,   0,   0 }  /* non-existent    */
 118         },
 119
 120         /* Port C */
 121         {       /*            conf      ppar psor pdir podr pdat */
 122                 { 0,             0,   0,   0,   0,   0 }, /* PC31            */
 123                 { 0,             0,   0,   0,   0,   0 }, /* PC30            */
 124                 { 0,             0,   0,   0,   0,   0 }, /* PC29            */
 125                 { 0,             0,   0,   0,   0,   0 }, /* PC28            */
 126                 { 0,             0,   0,   0,   0,   0 }, /* PC27            */
 127                 { 0,             0,   0,   0,   0,   0 }, /* PC26            */
 128                 { 1,             1,   0,   0,   0,   0 }, /* PC25 RxClk      */
 129                 { 1,             1,   0,   0,   0,   0 }, /* PC24 TxClk      */
 130                 { 0,             0,   0,   0,   0,   0 }, /* PC23            */
 131                 { 0,             0,   0,   0,   0,   0 }, /* PC22            */
 132                 { 0,             0,   0,   0,   0,   0 }, /* PC21            */
 133                 { 0,             0,   0,   0,   0,   0 }, /* PC20            */
 134                 { 0,             0,   0,   0,   0,   0 }, /* PC19            */
 135                 { 0,             0,   0,   0,   0,   0 }, /* PC18            */
 136                 { 0,             0,   0,   0,   0,   0 }, /* PC17            */
 137                 { 0,             0,   0,   0,   0,   0 }, /* PC16            */
 138                 { 0,             0,   0,   0,   0,   0 }, /* PC15            */
 139                 { 0,             0,   0,   0,   0,   0 }, /* PC14            */
 140                 { 0,             0,   0,   0,   0,   0 }, /* PC13            */
 141                 { 0,             0,   0,   0,   0,   0 }, /* PC12            */
 142                 { 0,             0,   0,   0,   0,   0 }, /* PC11            */
 143                 { 0,             0,   0,   0,   0,   0 }, /* PC10            */
 144                 { 1,             1,   0,   0,   0,   0 }, /* PC9  SCC4: CTS  */
 145                 { 1,             1,   0,   0,   0,   0 }, /* PC8  SCC4: CD   */
 146                 { 0,             0,   0,   0,   0,   0 }, /* PC7             */
 147                 { 0,             0,   0,   0,   0,   0 }, /* PC6             */
 148                 { 0,             0,   0,   0,   0,   0 }, /* PC5             */
 149                 { 0,             0,   0,   0,   0,   0 }, /* PC4             */
 150                 { 0,             0,   0,   0,   0,   0 }, /* PC3             */
 151                 { 0,             0,   0,   0,   0,   0 }, /* PC2             */
 152                 { 0,             0,   0,   0,   0,   0 }, /* PC1             */
 153                 { 0,             0,   0,   0,   0,   0 }, /* PC0             */
 154         },
 155
 156         /* Port D */
 157         {       /*            conf      ppar psor pdir podr pdat */
 158                 { 0,             0,   0,   0,   0,   0 }, /* PD31            */
 159                 { 0,             0,   0,   0,   0,   0 }, /* PD30            */
 160                 { 0,             0,   0,   0,   0,   0 }, /* PD29            */
 161                 { 0,             0,   0,   0,   0,   0 }, /* PD28            */
 162                 { 0,             0,   0,   0,   0,   0 }, /* PD27            */
 163                 { 0,             0,   0,   0,   0,   0 }, /* PD26            */
 164                 { 0,             0,   0,   0,   0,   0 }, /* PD25            */
 165                 { 0,             0,   0,   0,   0,   0 }, /* PD24            */
 166                 { 0,             0,   0,   0,   0,   0 }, /* PD23            */
 167                 { 1,             1,   0,   0,   0,   0 }, /* PD22 SCC4: RXD  */
 168                 { 1,             1,   0,   1,   0,   0 }, /* PD21 SCC4: TXD  */
 169                 { 1,             1,   0,   1,   0,   0 }, /* PD20 SCC4: RTS  */
 170                 { 0,             0,   0,   0,   0,   0 }, /* PD19            */
 171                 { 0,             0,   0,   0,   0,   0 }, /* PD18            */
 172                 { 0,             0,   0,   0,   0,   0 }, /* PD17            */
 173                 { 0,             0,   0,   0,   0,   0 }, /* PD16            */
 174 #if defined(CONFIG_HARD_I2C)
 175                 { 1,             1,   1,   0,   1,   0 }, /* PD15 I2C SDA    */
 176                 { 1,             1,   1,   0,   1,   0 }, /* PD14 I2C SCL    */
 177 #else
 178                 { 1,             0,   0,   0,   1,   1 }, /* PD15            */
 179                 { 1,             0,   0,   1,   1,   1 }, /* PD14            */
 180 #endif
 181                 { 0,             0,   0,   0,   0,   0 }, /* PD13            */
 182                 { 0,             0,   0,   0,   0,   0 }, /* PD12            */
 183                 { 0,             0,   0,   0,   0,   0 }, /* PD11            */
 184                 { 0,             0,   0,   0,   0,   0 }, /* PD10            */
 185                 { 0,             0,   0,   0,   0,   0 }, /* PD9             */
 186                 { 0,             0,   0,   0,   0,   0 }, /* PD8             */
 187                 { 0,             0,   0,   0,   0,   0 }, /* PD7             */
 188                 { 0,             0,   0,   0,   0,   0 }, /* PD6             */
 189                 { 0,             0,   0,   0,   0,   0 }, /* PD5             */
 190                 { 0,             0,   0,   0,   0,   0 }, /* PD4             */
 191                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 192                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 193                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 194                 { 0,             0,   0,   0,   0,   0 }  /* non-existent    */
 195         }
 196 };
 197
 198 /*
 199  * Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
 200  *
 201  * This routine performs standard 8260 initialization sequence
 202  * and calculates the available memory size. It may be called
 203  * several times to try different SDRAM configurations on both
 204  * 60x and local buses.
 205  */
 206 static long int try_init(memctl8260_t *memctl, ulong sdmr,
 207                                   ulong orx, uchar *base)
 208 {
 209         uchar c = 0xff;
 210         ulong maxsize, size;
 211         int i;
 212
 213         /*
 214          * We must be able to test a location outsize the maximum legal size
 215          * to find out THAT we are outside; but this address still has to be
 216          * mapped by the controller. That means, that the initial mapping has
 217          * to be (at least) twice as large as the maximum expected size.
 218          */
 219         maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
 220
 221         out_be32(&memctl->memc_or1, orx);
 222
 223         /*
 224          * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
 225          *
 226          * "At system reset, initialization software must set up the
 227          *  programmable parameters in the memory controller banks registers
 228          *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
 229          *  system software should execute the following initialization sequence
 230          *  for each SDRAM device.
 231          *
 232          *  1. Issue a PRECHARGE-ALL-BANKS command
 233          *  2. Issue eight CBR REFRESH commands
 234          *  3. Issue a MODE-SET command to initialize the mode register
 235          *
 236          *  The initial commands are executed by setting P/LSDMR[OP] and
 237          *  accessing the SDRAM with a single-byte transaction."
 238          *
 239          * The appropriate BRx/ORx registers have already been set when we
 240          * get here. The SDRAM can be accessed at the address
 241          * CONFIG_SYS_SDRAM_BASE.
 242          */
 243
 244         out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA);
 245         out_8(base, c);
 246
 247         out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR);
 248         for (i = 0; i < 8; i++)
 249                 out_8(base, c);
 250
 251         out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW);
 252         /* setting MR on address lines */
 253         out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c);
 254
 255         out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN);
 256         out_8(base, c);
 257
 258         size = get_ram_size((long *)base, maxsize);
 259         out_be32(&memctl->memc_or1, orx | ~(size - 1));
 260
 261         return size;
 262 }
 263
 264 #ifdef CONFIG_SYS_SDRAM_LIST
 265
 266 /*
 267  * If CONFIG_SYS_SDRAM_LIST is defined, we cycle through all SDRAM
 268  * configurations therein (should be from high to lower) to find the
 269  * one actually matching the current configuration.
 270  * CONFIG_SYS_PSDMR and CONFIG_SYS_OR1 will contain the base values which are
 271  * common among all possible configurations; values in CONFIG_SYS_SDRAM_LIST
 272  * (defined as the initialization value for the array of struct sdram_conf_s)
 273  * will then be ORed with such base values.
 274  */
 275
 276 struct sdram_conf_s {
 277         ulong size;
 278         int or1;
 279         int psdmr;
 280 };
 281
 282 static struct sdram_conf_s sdram_conf[] = CONFIG_SYS_SDRAM_LIST;
 283
 284 static long probe_sdram(memctl8260_t *memctl)
 285 {
 286         int n = 0;
 287         long psize = 0;
 288
 289         for (n = 0; n < ARRAY_SIZE(sdram_conf); psize = 0, n++) {
 290                 psize = try_init(memctl,
 291                         CONFIG_SYS_PSDMR | sdram_conf[n].psdmr,
 292                         CONFIG_SYS_OR1 | sdram_conf[n].or1,
 293                         (uchar *) CONFIG_SYS_SDRAM_BASE);
 294                 debug("Probing %ld bytes returned %ld\n",
 295                         sdram_conf[n].size, psize);
 296                 if (psize == sdram_conf[n].size)
 297                         break;
 298         }
 299         return psize;
 300 }
 301
 302 #else /* CONFIG_SYS_SDRAM_LIST */
 303
 304 static long probe_sdram(memctl8260_t *memctl)
 305 {
 306         return try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
 307                                         (uchar *) CONFIG_SYS_SDRAM_BASE);
 308 }
 309 #endif /* CONFIG_SYS_SDRAM_LIST */
 310
 311
 312 phys_size_t initdram(int board_type)
 313 {
 314         immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 315         memctl8260_t *memctl = &immap->im_memctl;
 316
 317         long psize;
 318
 319         out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT);
 320         out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
 321
 322 #ifndef CONFIG_SYS_RAMBOOT
 323         /* 60x SDRAM setup:
 324          */
 325         psize = probe_sdram(memctl);
 326 #endif /* CONFIG_SYS_RAMBOOT */
 327
 328         icache_enable();
 329
 330         return psize;
 331 }
 332
 333 int checkboard(void)
 334 {
 335 #if defined(CONFIG_MGCOGE)
 336         puts("Board: Keymile mgcoge");
 337 #else
 338         puts("Board: Keymile mgcoge3ne");
 339 #endif
 340         if (ethernet_present())
 341                 puts(" with PIGGY.");
 342         puts("\n");
 343         return 0;
 344 }
 345
 346 int last_stage_init(void)
 347 {
 348         struct bfticu_iomap *base =
 349                 (struct bfticu_iomap *)CONFIG_SYS_FPGA_BASE;
 350         u8 dip_switch;
 351
 352         dip_switch = in_8(&base->mswitch);
 353         dip_switch &= BFTICU_DIPSWITCH_MASK;
 354         /* dip switch 'full reset' or 'db erase' */
 355         if (dip_switch & 0x1 || dip_switch & 0x2) {
 356                 /* start bootloader */
 357                 puts("DIP:   Enabled\n");
 358                 setenv("actual_bank", "0");
 359         }
 360         set_km_env();
 361         return 0;
 362 }
 363
 364 #ifdef CONFIG_MGCOGE3NE
 365 static void set_pin(int state, unsigned long mask);
 366
 367 /*
 368  * For mgcoge3ne boards, the mgcoge3un control is controlled from
 369  * a GPIO line on the PPC CPU. If bobcatreset is set the line
 370  * will toggle once what forces the mgocge3un part to restart
 371  * immediately.
 372  */
 373 void handle_mgcoge3un_reset(void)
 374 {
 375         char *bobcatreset = getenv("bobcatreset");
 376         if (bobcatreset) {
 377                 if (strcmp(bobcatreset, "true") == 0) {
 378                         puts("Forcing bobcat reset\n");
 379                         set_pin(0, 0x00000004); /* clear PD29 to reset arm */
 380                         udelay(1000);
 381                         set_pin(1, 0x00000004);
 382                 } else
 383                         set_pin(1, 0x00000004); /* set PD29 to not reset arm */
 384         }
 385 }
 386 #endif
 387
 388 int ethernet_present(void)
 389 {
 390         struct km_bec_fpga *base =
 391                 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
 392
 393         return in_8(&base->bprth) & PIGGY_PRESENT;
 394 }
 395
 396 /*
 397  * Early board initalization.
 398  */
 399 int board_early_init_r(void)
 400 {
 401         struct km_bec_fpga *base =
 402                 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
 403
 404         /* setup the UPIOx */
 405         /* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
 406         out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED));
 407         /* SCC4 enable, halfduplex, FCC1 powerdown */
 408         out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA |
 409                 H_OPORTS_FCC1_PW_DWN));
 410
 411 #ifdef CONFIG_MGCOGE3NE
 412         handle_mgcoge3un_reset();
 413 #endif
 414         return 0;
 415 }
 416
 417 int hush_init_var(void)
 418 {
 419         ivm_read_eeprom();
 420         return 0;
 421 }
 422
 423 #define SDA_MASK        0x00010000
 424 #define SCL_MASK        0x00020000
 425
 426 static void set_pin(int state, unsigned long mask)
 427 {
 428         ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
 429
 430         if (state)
 431                 setbits_be32(&iop->pdat, mask);
 432         else
 433                 clrbits_be32(&iop->pdat, mask);
 434
 435         setbits_be32(&iop->pdir, mask);
 436 }
 437
 438 static int get_pin(unsigned long mask)
 439 {
 440         ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
 441
 442         clrbits_be32(&iop->pdir, mask);
 443         return 0 != (in_be32(&iop->pdat) & mask);
 444 }
 445
 446 void set_sda(int state)
 447 {
 448         set_pin(state, SDA_MASK);
 449 }
 450
 451 void set_scl(int state)
 452 {
 453         set_pin(state, SCL_MASK);
 454 }
 455
 456 int get_sda(void)
 457 {
 458         return get_pin(SDA_MASK);
 459 }
 460
 461 int get_scl(void)
 462 {
 463         return get_pin(SCL_MASK);
 464 }
 465
 466 #if defined(CONFIG_HARD_I2C)
 467 static void setports(int gpio)
 468 {
 469         ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
 470
 471         if (gpio) {
 472                 clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
 473                 clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
 474         } else {
 475                 setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
 476                 clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK));
 477                 setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
 478         }
 479 }
 480 #endif
 481 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
 482 void ft_board_setup(void *blob, bd_t *bd)
 483 {
 484         ft_cpu_setup(blob, bd);
 485 }
 486 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */