board/keymile/km83xx/km83xx.c

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *                    Dave Liu <daveliu@freescale.com>
   4  *
   5  * Copyright (C) 2007 Logic Product Development, Inc.
   6  *                    Peter Barada <peterb@logicpd.com>
   7  *
   8  * Copyright (C) 2007 MontaVista Software, Inc.
   9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10  *
  11  * (C) Copyright 2008 - 2010
  12  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  */
  19
  20 #include <common.h>
  21 #include <ioports.h>
  22 #include <mpc83xx.h>
  23 #include <i2c.h>
  24 #include <miiphy.h>
  25 #include <asm/io.h>
  26 #include <asm/mmu.h>
  27 #include <asm/processor.h>
  28 #include <pci.h>
  29 #include <libfdt.h>
  30 #include <post.h>
  31
  32 #include "../common/common.h"
  33
  34 const qe_iop_conf_t qe_iop_conf_tab[] = {
  35         /* port pin dir open_drain assign */
  36 #if defined(CONFIG_MPC8360)
  37         /* MDIO */
  38         {0,  1, 3, 0, 2}, /* MDIO */
  39         {0,  2, 1, 0, 1}, /* MDC */
  40
  41         /* UCC4 - UEC */
  42         {1, 14, 1, 0, 1}, /* TxD0 */
  43         {1, 15, 1, 0, 1}, /* TxD1 */
  44         {1, 20, 2, 0, 1}, /* RxD0 */
  45         {1, 21, 2, 0, 1}, /* RxD1 */
  46         {1, 18, 1, 0, 1}, /* TX_EN */
  47         {1, 26, 2, 0, 1}, /* RX_DV */
  48         {1, 27, 2, 0, 1}, /* RX_ER */
  49         {1, 24, 2, 0, 1}, /* COL */
  50         {1, 25, 2, 0, 1}, /* CRS */
  51         {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
  52         {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
  53
  54         /* DUART - UART2 */
  55         {5,  0, 1, 0, 2}, /* UART2_SOUT */
  56         {5,  2, 1, 0, 1}, /* UART2_RTS */
  57         {5,  3, 2, 0, 2}, /* UART2_SIN */
  58         {5,  1, 2, 0, 3}, /* UART2_CTS */
  59 #elif !defined(CONFIG_MPC8309)
  60         /* Local Bus */
  61         {0, 16, 1, 0, 3}, /* LA00 */
  62         {0, 17, 1, 0, 3}, /* LA01 */
  63         {0, 18, 1, 0, 3}, /* LA02 */
  64         {0, 19, 1, 0, 3}, /* LA03 */
  65         {0, 20, 1, 0, 3}, /* LA04 */
  66         {0, 21, 1, 0, 3}, /* LA05 */
  67         {0, 22, 1, 0, 3}, /* LA06 */
  68         {0, 23, 1, 0, 3}, /* LA07 */
  69         {0, 24, 1, 0, 3}, /* LA08 */
  70         {0, 25, 1, 0, 3}, /* LA09 */
  71         {0, 26, 1, 0, 3}, /* LA10 */
  72         {0, 27, 1, 0, 3}, /* LA11 */
  73         {0, 28, 1, 0, 3}, /* LA12 */
  74         {0, 29, 1, 0, 3}, /* LA13 */
  75         {0, 30, 1, 0, 3}, /* LA14 */
  76         {0, 31, 1, 0, 3}, /* LA15 */
  77
  78         /* MDIO */
  79         {3,  4, 3, 0, 2}, /* MDIO */
  80         {3,  5, 1, 0, 2}, /* MDC */
  81
  82         /* UCC4 - UEC */
  83         {1, 18, 1, 0, 1}, /* TxD0 */
  84         {1, 19, 1, 0, 1}, /* TxD1 */
  85         {1, 22, 2, 0, 1}, /* RxD0 */
  86         {1, 23, 2, 0, 1}, /* RxD1 */
  87         {1, 26, 2, 0, 1}, /* RxER */
  88         {1, 28, 2, 0, 1}, /* Rx_DV */
  89         {1, 30, 1, 0, 1}, /* TxEN */
  90         {1, 31, 2, 0, 1}, /* CRS */
  91         {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
  92 #endif
  93
  94         /* END of table */
  95         {0,  0, 0, 0, QE_IOP_TAB_END},
  96 };
  97
  98 #if defined(CONFIG_SUVD3)
  99 const uint upma_table[] = {
 100         0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
 101         0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */
 102         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */
 103         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */
 104         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */
 105         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */
 106         0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */
 107         0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
 108         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */
 109         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */
 110         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */
 111         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */
 112         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */
 113         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */
 114         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */
 115         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01  /* Words 60 to 63 */
 116 };
 117 #endif
 118
 119 static int piggy_present(void)
 120 {
 121         struct km_bec_fpga __iomem *base =
 122                 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
 123
 124         return in_8(&base->bprth) & PIGGY_PRESENT;
 125 }
 126
 127 #if defined(CONFIG_KMVECT1)
 128 int ethernet_present(void)
 129 {
 130         /* ethernet port connected to simple switch without piggy */
 131         return 1;
 132 }
 133 #else
 134 int ethernet_present(void)
 135 {
 136         return piggy_present();
 137 }
 138 #endif
 139
 140
 141 int board_early_init_r(void)
 142 {
 143         struct km_bec_fpga *base =
 144                 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
 145 #if defined(CONFIG_SUVD3)
 146         immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 147         fsl_lbc_t *lbc = &immap->im_lbc;
 148         u32 *mxmr = &lbc->mamr;
 149 #endif
 150
 151 #if defined(CONFIG_MPC8360)
 152         unsigned short  svid;
 153         /*
 154          * Because of errata in the UCCs, we have to write to the reserved
 155          * registers to slow the clocks down.
 156          */
 157         svid =  SVR_REV(mfspr(SVR));
 158         switch (svid) {
 159         case 0x0020:
 160                 /*
 161                  * MPC8360ECE.pdf QE_ENET10 table 4:
 162                  * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
 163                  * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
 164                  */
 165                 setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
 166                 break;
 167         case 0x0021:
 168                 /*
 169                  * MPC8360ECE.pdf QE_ENET10 table 4:
 170                  * IMMR + 0x14AC[24:27] = 1010
 171                  */
 172                 clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
 173                         0x00000050, 0x000000a0);
 174                 break;
 175         }
 176 #endif
 177
 178         /* enable the PHY on the PIGGY */
 179         setbits_8(&base->pgy_eth, 0x01);
 180         /* enable the Unit LED (green) */
 181         setbits_8(&base->oprth, WRL_BOOT);
 182         /* enable Application Buffer */
 183         setbits_8(&base->oprtl, OPRTL_XBUFENA);
 184
 185 #if defined(CONFIG_SUVD3)
 186         /* configure UPMA for APP1 */
 187         upmconfig(UPMA, (uint *) upma_table,
 188                 sizeof(upma_table) / sizeof(uint));
 189         out_be32(mxmr, CONFIG_SYS_MAMR);
 190 #endif
 191         return 0;
 192 }
 193
 194 int misc_init_r(void)
 195 {
 196         return 0;
 197 }
 198
 199 #if defined(CONFIG_KMVECT1)
 200 #include <mv88e6352.h>
 201 /* Marvell MV88E6122 switch configuration */
 202 static struct mv88e_sw_reg extsw_conf[] = {
 203         /* port 1, FRONT_MDI, autoneg */
 204         { PORT(1), PORT_PHY, NO_SPEED_FOR },
 205         { PORT(1), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
 206         { PHY(1), PHY_1000_CTRL, NO_ADV },
 207         { PHY(1), PHY_SPEC_CTRL, AUTO_MDIX_EN },
 208         { PHY(1), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
 209                 FULL_DUPLEX },
 210         /* port 2, unused */
 211         { PORT(2), PORT_CTRL, PORT_DIS },
 212         { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
 213         { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
 214         /* port 3, BP_MII (CPU), PHY mode, 100BASE */
 215         { PORT(3), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
 216         /* port 4, ESTAR to slot 11, SerDes, 1000BASE-X */
 217         { PORT(4), PORT_STATUS, NO_PHY_DETECT },
 218         { PORT(4), PORT_PHY, SPEED_1000_FOR },
 219         { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
 220         /* port 5, ESTAR to slot 13, SerDes, 1000BASE-X */
 221         { PORT(5), PORT_STATUS, NO_PHY_DETECT },
 222         { PORT(5), PORT_PHY, SPEED_1000_FOR },
 223         { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
 224         /*
 225          * Errata Fix: 1.9V Output from Internal 1.8V Regulator,
 226          * acc . MV-S300889-00D.pdf , clause 4.5
 227          */
 228         { PORT(5), 0x1A, 0xADB1 },
 229         /* port 6, unused, this port has no phy */
 230         { PORT(6), PORT_CTRL, PORT_DIS },
 231 };
 232 #endif
 233
 234 int last_stage_init(void)
 235 {
 236 #if defined(CONFIG_KMVECT1)
 237         struct km_bec_fpga __iomem *base =
 238                 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
 239         u8 tmp_reg;
 240
 241         /* Release mv88e6122 from reset */
 242         tmp_reg = in_8(&base->res1[0]) | 0x10; /* DIRECT3 register */
 243         out_8(&base->res1[0], tmp_reg);        /* GP28 as output */
 244         tmp_reg = in_8(&base->gprt3) | 0x10;   /* GP28 to high */
 245         out_8(&base->gprt3, tmp_reg);
 246
 247         /* configure MV88E6122 switch */
 248         char *name = "UEC2";
 249
 250         if (miiphy_set_current_dev(name))
 251                 return 0;
 252
 253         mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
 254                 ARRAY_SIZE(extsw_conf));
 255
 256         mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
 257
 258         if (piggy_present()) {
 259                 setenv("ethact", "UEC2");
 260                 setenv("netdev", "eth1");
 261                 puts("using PIGGY for network boot\n");
 262         } else {
 263                 setenv("netdev", "eth0");
 264                 puts("using frontport for network boot\n");
 265         }
 266 #endif
 267
 268 #if defined(CONFIG_KMCOGE5NE)
 269         struct bfticu_iomap *base =
 270                 (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
 271         u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
 272
 273         if (dip_switch != 0) {
 274                 /* start bootloader */
 275                 puts("DIP:   Enabled\n");
 276                 setenv("actual_bank", "0");
 277         }
 278 #endif
 279         set_km_env();
 280         return 0;
 281 }
 282
 283 int fixed_sdram(void)
 284 {
 285         immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 286         u32 msize = 0;
 287         u32 ddr_size;
 288         u32 ddr_size_log2;
 289
 290         out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
 291         out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
 292         out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
 293         out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
 294         out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
 295         out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
 296         out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
 297         out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
 298         out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
 299         out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
 300         out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
 301         out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
 302         out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
 303         udelay(200);
 304         setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
 305
 306         msize = CONFIG_SYS_DDR_SIZE << 20;
 307         disable_addr_trans();
 308         msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
 309         enable_addr_trans();
 310         msize /= (1024 * 1024);
 311         if (CONFIG_SYS_DDR_SIZE != msize) {
 312                 for (ddr_size = msize << 20, ddr_size_log2 = 0;
 313                         (ddr_size > 1);
 314                         ddr_size = ddr_size >> 1, ddr_size_log2++)
 315                         if (ddr_size & 1)
 316                                 return -1;
 317                 out_be32(&im->sysconf.ddrlaw[0].ar,
 318                         (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
 319                 out_be32(&im->ddr.csbnds[0].csbnds,
 320                         (((msize / 16) - 1) & 0xff));
 321         }
 322
 323         return msize;
 324 }
 325
 326 phys_size_t initdram(int board_type)
 327 {
 328         immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 329         u32 msize = 0;
 330
 331         if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
 332                 return -1;
 333
 334         out_be32(&im->sysconf.ddrlaw[0].bar,
 335                 CONFIG_SYS_DDR_BASE & LAWBAR_BAR);
 336         msize = fixed_sdram();
 337
 338 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 339         /*
 340          * Initialize DDR ECC byte
 341          */
 342         ddr_enable_ecc(msize * 1024 * 1024);
 343 #endif
 344
 345         /* return total bus SDRAM size(bytes)  -- DDR */
 346         return msize * 1024 * 1024;
 347 }
 348
 349 int checkboard(void)
 350 {
 351         puts("Board: Keymile " CONFIG_KM_BOARD_NAME);
 352
 353         if (piggy_present())
 354                 puts(" with PIGGY.");
 355         puts("\n");
 356         return 0;
 357 }
 358
 359 #if defined(CONFIG_OF_BOARD_SETUP)
 360 void ft_board_setup(void *blob, bd_t *bd)
 361 {
 362         ft_cpu_setup(blob, bd);
 363 }
 364 #endif
 365
 366 #if defined(CONFIG_HUSH_INIT_VAR)
 367 int hush_init_var(void)
 368 {
 369         ivm_read_eeprom();
 370         return 0;
 371 }
 372 #endif
 373
 374 #if defined(CONFIG_POST)
 375 int post_hotkeys_pressed(void)
 376 {
 377         int testpin = 0;
 378         struct km_bec_fpga *base =
 379                 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
 380         int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
 381         testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
 382         debug("post_hotkeys_pressed: %d\n", !testpin);
 383         return testpin;
 384 }
 385
 386 ulong post_word_load(void)
 387 {
 388         void* addr = (ulong *) (CPM_POST_WORD_ADDR);
 389         debug("post_word_load 0x%08lX:  0x%08X\n", (ulong)addr, in_le32(addr));
 390         return in_le32(addr);
 391
 392 }
 393 void post_word_store(ulong value)
 394 {
 395         void* addr = (ulong *) (CPM_POST_WORD_ADDR);
 396         debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
 397         out_le32(addr, value);
 398 }
 399
 400 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 401 {
 402         *vstart = CONFIG_SYS_MEMTEST_START;
 403         *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
 404         debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
 405
 406         return 0;
 407 }
 408 #endif