board/laird/wb45n/wb45n.c

   1 /*
   2  *
   3  * SPDX-License-Identifier: GPL-2.0+
   4  */
   5
   6 #include <common.h>
   7 #include <asm/io.h>
   8 #include <asm/arch/at91sam9x5_matrix.h>
   9 #include <asm/arch/at91sam9_smc.h>
  10 #include <asm/arch/at91_common.h>
  11 #include <asm/arch/at91_rstc.h>
  12 #include <asm/arch/clk.h>
  13 #include <asm/arch/gpio.h>
  14 #include <net.h>
  15 #include <netdev.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 /* ------------------------------------------------------------------------- */
  20 /*
  21  * Miscelaneous platform dependent initialisations
  22  */
  23 static void wb45n_nand_hw_init(void)
  24 {
  25         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  26         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  27         unsigned long csa;
  28
  29         csa = readl(&matrix->ebicsa);
  30         /* Enable CS3 */
  31         csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
  32         /* NAND flash on D0 */
  33         csa &= ~AT91_MATRIX_NFD0_ON_D16;
  34         writel(csa, &matrix->ebicsa);
  35
  36         /* Configure SMC CS3 for NAND/SmartMedia */
  37         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  38                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  39                &smc->cs[3].setup);
  40         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  41                AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
  42                &smc->cs[3].pulse);
  43         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
  44                &smc->cs[3].cycle);
  45         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  46                AT91_SMC_MODE_EXNW_DISABLE |
  47                AT91_SMC_MODE_DBW_8 |
  48                AT91_SMC_MODE_TDF_CYCLE(1), &smc->cs[3].mode);
  49
  50         at91_periph_clk_enable(ATMEL_ID_PIOCD);
  51
  52         /* Configure RDY/BSY */
  53         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  54         /* Enable NandFlash */
  55         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  56         /* Disable Flash Write Protect Line */
  57         at91_set_gpio_output(AT91_PIN_PD10, 1);
  58
  59         at91_set_a_periph(AT91_PIO_PORTD, 0, 1);        /* NAND OE */
  60         at91_set_a_periph(AT91_PIO_PORTD, 1, 1);        /* NAND WE */
  61         at91_set_a_periph(AT91_PIO_PORTD, 2, 1);        /* NAND ALE */
  62         at91_set_a_periph(AT91_PIO_PORTD, 3, 1);        /* NAND CLE */
  63 }
  64
  65 static void wb45n_gpio_hw_init(void)
  66 {
  67
  68         /* Configure wifi gpio CHIP_PWD_L */
  69         at91_set_gpio_output(AT91_PIN_PA28, 0);
  70
  71         /* Setup USB pins */
  72         at91_set_gpio_input(AT91_PIN_PB11, 0);
  73         at91_set_gpio_output(AT91_PIN_PB12, 0);
  74
  75         /* IRQ pin, pullup, deglitch */
  76         at91_set_gpio_input(AT91_PIN_PB18, 1);
  77         at91_set_gpio_deglitch(AT91_PIN_PB18, 1);
  78 }
  79
  80 int board_eth_init(bd_t *bis)
  81 {
  82         int rc = 0;
  83
  84         if (has_emac0())
  85                 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
  86
  87         return rc;
  88 }
  89
  90 int board_early_init_f(void)
  91 {
  92         at91_seriald_hw_init();
  93         return 0;
  94 }
  95
  96 int board_init(void)
  97 {
  98         /* address of boot parameters */
  99         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 100
 101         wb45n_gpio_hw_init();
 102
 103         wb45n_nand_hw_init();
 104
 105         at91_macb_hw_init();
 106
 107         return 0;
 108 }
 109
 110 int dram_init(void)
 111 {
 112         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 113                                     CONFIG_SYS_SDRAM_SIZE);
 114         return 0;
 115 }
 116
 117 #if defined(CONFIG_SPL_BUILD)
 118 #include <spl.h>
 119 #include <nand.h>
 120
 121 void at91_spl_board_init(void)
 122 {
 123         /* Setup GPIO first */
 124         wb45n_gpio_hw_init();
 125
 126         /* Bring up NAND */
 127         wb45n_nand_hw_init();
 128 }
 129
 130 void matrix_init(void)
 131 {
 132         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 133         unsigned long csa;
 134
 135         csa = readl(&matrix->ebicsa);
 136         /* Pull ups on D0 - D16 */
 137         csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
 138         csa |= AT91_MATRIX_EBI_DBPD_OFF;
 139         /* Normal drive strength */
 140         csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
 141         /* Multi-port off */
 142         csa &= ~AT91_MATRIX_MP_ON;
 143         writel(csa, &matrix->ebicsa);
 144 }
 145
 146 #include <asm/arch/atmel_mpddrc.h>
 147 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 148 {
 149         ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM);
 150
 151         ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 152                     ATMEL_MPDDRC_CR_NR_ROW_13 |
 153                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 154                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 155                     ATMEL_MPDDRC_CR_DQMS_SHARED);
 156
 157         ddr2->rtr = 0x411;
 158
 159         ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 160                       2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 161                       2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 162                       8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 163                       2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 164                       2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 165                       2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 166                       2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 167
 168         ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
 169                       200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 170                       19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 171                       18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
 172
 173         ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
 174                       2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 175                       3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 176                       7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 177                       2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
 178 }
 179
 180 void mem_init(void)
 181 {
 182         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 183         struct atmel_mpddrc_config ddr2;
 184         unsigned long csa;
 185
 186         ddr2_conf(&ddr2);
 187
 188         /* enable DDR2 clock */
 189         at91_system_clk_enable(AT91_PMC_DDR);
 190
 191         /* Chip select 1 is for DDR2/SDRAM */
 192         csa = readl(&matrix->ebicsa);
 193         csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
 194         writel(csa, &matrix->ebicsa);
 195
 196         /* DDRAM2 Controller initialize */
 197         ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
 198 }
 199 #endif