3 * Logic Product Development <www.logicpd.com>
6 * Peter Barada <peter.barada@logicpd.com>
8 * Derived from Beagle Board and 3430 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * SPDX-License-Identifier: GPL-2.0+
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/mux.h>
25 #include <asm/arch/mem.h>
26 #include <asm/arch/sys_proto.h>
28 #include <asm/mach-types.h>
29 #include <linux/mtd/nand.h>
30 #include <asm/omap_musb.h>
31 #include <asm/errno.h>
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
34 #include <linux/usb/musb.h>
35 #include "omap3logic.h"
37 DECLARE_GLOBAL_DATA_PTR
;
39 #define CONTROL_WKUP_CTRL 0x48002a5c
40 #define GPIO_IO_PWRDNZ (1 << 6)
41 #define PBIASLITEVMODE1 (1 << 8)
44 * two dimensional array of strucures containining board name and Linux
45 * machine IDs; row it selected based on CPU column is slected based
46 * on hsusb0_data5 pin having a pulldown resistor
49 static const struct ns16550_platdata omap3logic_serial
= {
50 .base
= OMAP34XX_UART1
,
52 .clock
= V_NS16550_CLK
55 U_BOOT_DEVICE(omap3logic_uart
) = {
60 static struct board_id
{
66 .name
= "OMAP35xx SOM LV",
67 .machine_id
= MACH_TYPE_OMAP3530_LV_SOM
,
70 .name
= "OMAP35xx Torpedo",
71 .machine_id
= MACH_TYPE_OMAP3_TORPEDO
,
76 .name
= "DM37xx SOM LV",
77 .machine_id
= MACH_TYPE_DM3730_SOM_LV
,
80 .name
= "DM37xx Torpedo",
81 .machine_id
= MACH_TYPE_DM3730_TORPEDO
,
86 #ifdef CONFIG_SPL_OS_BOOT
87 int spl_start_uboot(void)
89 /* break into full u-boot on 'c' */
90 return serial_tstc() && serial_getc() == 'c';
94 #if defined(CONFIG_SPL_BUILD)
96 * Routine: get_board_mem_timings
97 * Description: If we use SPL then there is no x-loader nor config header
98 * so we have to setup the DDR timings ourself on the first bank. This
99 * provides the timing values back to the function that configures
102 void get_board_mem_timings(struct board_sdrc_timings
*timings
)
104 timings
->mr
= MICRON_V_MR_165
;
106 timings
->mcfg
= MICRON_V_MCFG_200(256 << 20);
107 timings
->ctrla
= MICRON_V_ACTIMA_200
;
108 timings
->ctrlb
= MICRON_V_ACTIMB_200
;
109 timings
->rfr_ctrl
= SDP_3430_SDRC_RFR_CTRL_200MHz
;
113 #ifdef CONFIG_USB_MUSB_OMAP2PLUS
114 static struct musb_hdrc_config musb_config
= {
121 static struct omap_musb_board_data musb_board_data
= {
122 .interface_type
= MUSB_INTERFACE_ULPI
,
125 static struct musb_hdrc_platform_data musb_plat
= {
126 #if defined(CONFIG_USB_MUSB_HOST)
128 #elif defined(CONFIG_USB_MUSB_GADGET)
129 .mode
= MUSB_PERIPHERAL
,
131 #error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
133 .config
= &musb_config
,
135 .platform_ops
= &omap2430_ops
,
136 .board_data
= &musb_board_data
,
142 * Routine: misc_init_r
143 * Description: Configure board specific parts
145 int misc_init_r(void)
147 twl4030_power_init();
148 omap_die_id_display();
150 #ifdef CONFIG_USB_MUSB_OMAP2PLUS
151 musb_register(&musb_plat
, &musb_board_data
, (void *)MUSB_BASE
);
158 * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
160 #define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */
163 * Routine: board_init
164 * Description: Early hardware init.
168 struct board_id
*board
;
171 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
173 /* boot param addr */
174 gd
->bd
->bi_boot_params
= (OMAP34XX_SDRC_CS0
+ 0x100);
177 * To identify between a SOM LV and Torpedo module,
178 * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
179 * Drive the pin (and let it soak), then read it back.
180 * If the pin is still high its a Torpedo. If low its a SOM LV
183 /* Mux hsusb0_data5 as a GPIO */
184 MUX_VAL(CP(HSUSB0_DATA5
), (IEN
| PTD
| DIS
| M4
));
186 if (gpio_request(BOARD_ID_GPIO
, "husb0_data5.gpio_189") == 0) {
189 * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV
190 * will drain the voltage.
192 gpio_direction_output(BOARD_ID_GPIO
, 0);
193 gpio_set_value(BOARD_ID_GPIO
, 1);
195 /* Let it soak for a bit */
199 * Read state of BOARD_ID_GPIO as an input and if its set.
200 * If so the board is a Torpedo
202 gpio_direction_input(BOARD_ID_GPIO
);
203 val
= gpio_get_value(BOARD_ID_GPIO
);
204 gpio_free(BOARD_ID_GPIO
);
206 board
= &boards
[!!(get_cpu_family() == CPU_OMAP36XX
)][!!val
];
207 printf("Board: %s\n", board
->name
);
209 /* Set the machine_id passed to Linux */
210 gd
->bd
->bi_arch_number
= board
->machine_id
;
213 /* restore hsusb0_data5 pin as hsusb0_data5 */
214 MUX_VAL(CP(HSUSB0_DATA5
), (IEN
| PTD
| DIS
| M0
));
219 #ifdef CONFIG_BOARD_LATE_INIT
220 int board_late_init(void)
222 switch (gd
->bd
->bi_arch_number
) {
223 case MACH_TYPE_DM3730_TORPEDO
:
224 setenv("fdtimage", "logicpd-torpedo-37xx-devkit.dtb");
226 case MACH_TYPE_DM3730_SOM_LV
:
227 setenv("fdtimage", "logicpd-som-lv-37xx-devkit.dtb");
229 case MACH_TYPE_OMAP3_TORPEDO
:
230 setenv("fdtimage", "logicpd-torpedo-35xx-devkit.dtb");
232 case MACH_TYPE_OMAP3530_LV_SOM
:
233 setenv("fdtimage", "logicpd-som-lv-35xx-devkit.dtb");
236 /* unknown machine type */
243 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
244 int board_mmc_init(bd_t
*bis
)
246 return omap_mmc_init(0, 0, 0, -1, -1);
250 #if defined(CONFIG_GENERIC_MMC)
251 void board_mmc_power_init(void)
253 twl4030_power_mmc_init(0);
257 #ifdef CONFIG_SMC911X
258 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
259 static const u32 gpmc_lan92xx_config
[] = {
260 NET_LAN92XX_GPMC_CONFIG1
,
261 NET_LAN92XX_GPMC_CONFIG2
,
262 NET_LAN92XX_GPMC_CONFIG3
,
263 NET_LAN92XX_GPMC_CONFIG4
,
264 NET_LAN92XX_GPMC_CONFIG5
,
265 NET_LAN92XX_GPMC_CONFIG6
,
268 int board_eth_init(bd_t
*bis
)
270 enable_gpmc_cs_config(gpmc_lan92xx_config
, &gpmc_cfg
->cs
[1],
271 CONFIG_SMC911X_BASE
, GPMC_SIZE_16M
);
273 return smc911x_initialize(0, CONFIG_SMC911X_BASE
);
279 * IDIS - Input Disable
280 * PTD - Pull type Down
282 * DIS - Pull type selection is inactive
283 * EN - Pull type selection is active
285 * The commented string gives the final mux configuration for that pin
289 * Routine: set_muxconf_regs
290 * Description: Setting up the configuration Mux registers specific to the
291 * hardware. Many pins need to be moved from protect to primary
294 void set_muxconf_regs(void)
296 MUX_VAL(CP(SDRC_D0
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D0*/
297 MUX_VAL(CP(SDRC_D1
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D1*/
298 MUX_VAL(CP(SDRC_D2
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D2*/
299 MUX_VAL(CP(SDRC_D3
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D3*/
300 MUX_VAL(CP(SDRC_D4
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D4*/
301 MUX_VAL(CP(SDRC_D5
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D5*/
302 MUX_VAL(CP(SDRC_D6
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D6*/
303 MUX_VAL(CP(SDRC_D7
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D7*/
304 MUX_VAL(CP(SDRC_D8
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D8*/
305 MUX_VAL(CP(SDRC_D9
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D9*/
306 MUX_VAL(CP(SDRC_D10
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D10*/
307 MUX_VAL(CP(SDRC_D11
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D11*/
308 MUX_VAL(CP(SDRC_D12
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D12*/
309 MUX_VAL(CP(SDRC_D13
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D13*/
310 MUX_VAL(CP(SDRC_D14
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D14*/
311 MUX_VAL(CP(SDRC_D15
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D15*/
312 MUX_VAL(CP(SDRC_D16
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D16*/
313 MUX_VAL(CP(SDRC_D17
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D17*/
314 MUX_VAL(CP(SDRC_D18
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D18*/
315 MUX_VAL(CP(SDRC_D19
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D19*/
316 MUX_VAL(CP(SDRC_D20
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D20*/
317 MUX_VAL(CP(SDRC_D21
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D21*/
318 MUX_VAL(CP(SDRC_D22
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D22*/
319 MUX_VAL(CP(SDRC_D23
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D23*/
320 MUX_VAL(CP(SDRC_D24
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D24*/
321 MUX_VAL(CP(SDRC_D25
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D25*/
322 MUX_VAL(CP(SDRC_D26
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D26*/
323 MUX_VAL(CP(SDRC_D27
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D27*/
324 MUX_VAL(CP(SDRC_D28
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D28*/
325 MUX_VAL(CP(SDRC_D29
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D29*/
326 MUX_VAL(CP(SDRC_D30
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D30*/
327 MUX_VAL(CP(SDRC_D31
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D31*/
328 MUX_VAL(CP(SDRC_CLK
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_CLK*/
329 MUX_VAL(CP(SDRC_DQS0
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_DQS0*/
330 MUX_VAL(CP(SDRC_DQS1
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_DQS1*/
331 MUX_VAL(CP(SDRC_DQS2
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_DQS2*/
332 MUX_VAL(CP(SDRC_DQS3
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_DQS3*/
333 MUX_VAL(CP(SDRC_CKE0
), (IDIS
| PTU
| EN
| M0
)); /*SDRC_CKE0*/
334 MUX_VAL(CP(SDRC_CKE1
), (IDIS
| PTD
| DIS
| M7
)); /*SDRC_CKE1*/
336 MUX_VAL(CP(GPMC_A1
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A1*/
337 MUX_VAL(CP(GPMC_A2
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A2*/
338 MUX_VAL(CP(GPMC_A3
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A3*/
339 MUX_VAL(CP(GPMC_A4
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A4*/
340 MUX_VAL(CP(GPMC_A5
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A5*/
341 MUX_VAL(CP(GPMC_A6
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A6*/
342 MUX_VAL(CP(GPMC_A7
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A7*/
343 MUX_VAL(CP(GPMC_A8
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A8*/
344 MUX_VAL(CP(GPMC_A9
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A9*/
345 MUX_VAL(CP(GPMC_A10
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A10*/
346 MUX_VAL(CP(GPMC_D0
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D0*/
347 MUX_VAL(CP(GPMC_D1
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D1*/
348 MUX_VAL(CP(GPMC_D2
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D2*/
349 MUX_VAL(CP(GPMC_D3
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D3*/
350 MUX_VAL(CP(GPMC_D4
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D4*/
351 MUX_VAL(CP(GPMC_D5
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D5*/
352 MUX_VAL(CP(GPMC_D6
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D6*/
353 MUX_VAL(CP(GPMC_D7
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D7*/
354 MUX_VAL(CP(GPMC_D8
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D8*/
355 MUX_VAL(CP(GPMC_D9
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D9*/
356 MUX_VAL(CP(GPMC_D10
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D10*/
357 MUX_VAL(CP(GPMC_D11
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D11*/
358 MUX_VAL(CP(GPMC_D12
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D12*/
359 MUX_VAL(CP(GPMC_D13
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D13*/
360 MUX_VAL(CP(GPMC_D14
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D14*/
361 MUX_VAL(CP(GPMC_D15
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D15*/
362 MUX_VAL(CP(GPMC_NCS0
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_nCS0*/
363 MUX_VAL(CP(GPMC_NCS1
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_nCS1*/
364 MUX_VAL(CP(GPMC_NCS2
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_nCS2*/
365 MUX_VAL(CP(GPMC_NCS3
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_nCS3*/
366 MUX_VAL(CP(GPMC_NCS4
), (IEN
| PTU
| EN
| M0
)); /*GPMC_nCS4*/
367 MUX_VAL(CP(GPMC_NCS5
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_nCS5*/
368 MUX_VAL(CP(GPMC_NCS6
), (IEN
| PTU
| EN
| M0
)); /*GPMC_nCS6*/
369 MUX_VAL(CP(GPMC_NCS7
), (IEN
| PTU
| EN
| M0
)); /*GPMC_nCS7*/
370 MUX_VAL(CP(GPMC_CLK
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_CLK*/
371 MUX_VAL(CP(GPMC_NADV_ALE
), (IDIS
| PTD
| DIS
| M0
)); /*GPMC_nADV_ALE*/
372 MUX_VAL(CP(GPMC_NOE
), (IDIS
| PTD
| DIS
| M0
)); /*GPMC_nOE*/
373 MUX_VAL(CP(GPMC_NWE
), (IDIS
| PTD
| DIS
| M0
)); /*GPMC_nWE*/
374 MUX_VAL(CP(GPMC_NBE0_CLE
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_nBE0_CLE*/
375 MUX_VAL(CP(GPMC_NBE1
), (IEN
| PTU
| EN
| M0
)); /*GPMC_nBE1*/
376 MUX_VAL(CP(GPMC_NWP
), (IEN
| PTD
| DIS
| M0
)); /*GPMC_nWP*/
377 MUX_VAL(CP(GPMC_WAIT0
), (IEN
| PTU
| EN
| M0
)); /*GPMC_WAIT0*/
378 MUX_VAL(CP(GPMC_WAIT1
), (IEN
| PTU
| EN
| M0
)); /*GPMC_WAIT1*/
379 MUX_VAL(CP(GPMC_WAIT2
), (IEN
| PTU
| EN
| M4
)); /*GPIO_64*/
380 MUX_VAL(CP(GPMC_WAIT3
), (IEN
| PTU
| EN
| M0
)); /*GPMC_WAIT3*/
382 MUX_VAL(CP(CAM_HS
), (IEN
| PTU
| EN
| M0
)); /*CAM_HS */
383 MUX_VAL(CP(CAM_VS
), (IEN
| PTU
| EN
| M0
)); /*CAM_VS */
384 MUX_VAL(CP(CAM_XCLKA
), (IDIS
| PTD
| DIS
| M0
)); /*CAM_XCLKA*/
385 MUX_VAL(CP(CAM_PCLK
), (IEN
| PTU
| EN
| M0
)); /*CAM_PCLK*/
386 MUX_VAL(CP(CAM_FLD
), (IDIS
| PTD
| DIS
| M4
)); /*GPIO_98*/
387 MUX_VAL(CP(CAM_D0
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D0*/
388 MUX_VAL(CP(CAM_D1
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D1*/
389 MUX_VAL(CP(CAM_D2
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D2*/
390 MUX_VAL(CP(CAM_D3
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D3*/
391 MUX_VAL(CP(CAM_D4
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D4*/
392 MUX_VAL(CP(CAM_D5
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D5*/
393 MUX_VAL(CP(CAM_D6
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D6*/
394 MUX_VAL(CP(CAM_D7
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D7*/
395 MUX_VAL(CP(CAM_D8
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D8*/
396 MUX_VAL(CP(CAM_D9
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D9*/
397 MUX_VAL(CP(CAM_D10
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D10*/
398 MUX_VAL(CP(CAM_D11
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D11*/
399 MUX_VAL(CP(CAM_XCLKB
), (IDIS
| PTD
| DIS
| M0
)); /*CAM_XCLKB*/
400 MUX_VAL(CP(CAM_WEN
), (IEN
| PTD
| DIS
| M4
)); /*GPIO_167*/
401 MUX_VAL(CP(CAM_STROBE
), (IDIS
| PTD
| DIS
| M0
)); /*CAM_STROBE*/
403 MUX_VAL(CP(CSI2_DX0
), (IEN
| PTD
| DIS
| M0
)); /*CSI2_DX0*/
404 MUX_VAL(CP(CSI2_DY0
), (IEN
| PTD
| DIS
| M0
)); /*CSI2_DY0*/
405 MUX_VAL(CP(CSI2_DX1
), (IEN
| PTD
| DIS
| M0
)); /*CSI2_DX1*/
406 MUX_VAL(CP(CSI2_DY1
), (IEN
| PTD
| DIS
| M0
)); /*CSI2_DY1*/
408 MUX_VAL(CP(MCBSP2_FSX
), (IEN
| PTD
| DIS
| M0
)); /*McBSP2_FSX*/
409 MUX_VAL(CP(MCBSP2_CLKX
), (IEN
| PTD
| DIS
| M0
)); /*McBSP2_CLKX*/
410 MUX_VAL(CP(MCBSP2_DR
), (IEN
| PTD
| DIS
| M0
)); /*McBSP2_DR*/
411 MUX_VAL(CP(MCBSP2_DX
), (IDIS
| PTD
| DIS
| M0
)); /*McBSP2_DX*/
413 MUX_VAL(CP(MMC1_CLK
), (IDIS
| PTU
| EN
| M0
)); /*MMC1_CLK*/
414 MUX_VAL(CP(MMC1_CMD
), (IEN
| PTU
| EN
| M0
)); /*MMC1_CMD*/
415 MUX_VAL(CP(MMC1_DAT0
), (IEN
| PTU
| EN
| M0
)); /*MMC1_DAT0*/
416 MUX_VAL(CP(MMC1_DAT1
), (IEN
| PTU
| EN
| M0
)); /*MMC1_DAT1*/
417 MUX_VAL(CP(MMC1_DAT2
), (IEN
| PTU
| EN
| M0
)); /*MMC1_DAT2*/
418 MUX_VAL(CP(MMC1_DAT3
), (IEN
| PTU
| EN
| M0
)); /*MMC1_DAT3*/
419 MUX_VAL(CP(MMC1_DAT4
), (IEN
| PTU
| EN
| M0
)); /*MMC1_DAT4*/
420 MUX_VAL(CP(MMC1_DAT5
), (IEN
| PTU
| EN
| M0
)); /*MMC1_DAT5*/
421 MUX_VAL(CP(MMC1_DAT6
), (IEN
| PTU
| EN
| M0
)); /*MMC1_DAT6*/
422 MUX_VAL(CP(MMC1_DAT7
), (IEN
| PTU
| EN
| M0
)); /*MMC1_DAT7*/
424 MUX_VAL(CP(MMC2_CLK
), (IEN
| PTD
| DIS
| M0
)); /*MMC2_CLK*/
425 MUX_VAL(CP(MMC2_CMD
), (IEN
| PTU
| EN
| M0
)); /*MMC2_CMD*/
426 MUX_VAL(CP(MMC2_DAT0
), (IEN
| PTU
| EN
| M0
)); /*MMC2_DAT0*/
427 MUX_VAL(CP(MMC2_DAT1
), (IEN
| PTU
| EN
| M0
)); /*MMC2_DAT1*/
428 MUX_VAL(CP(MMC2_DAT2
), (IEN
| PTU
| EN
| M0
)); /*MMC2_DAT2*/
429 MUX_VAL(CP(MMC2_DAT3
), (IEN
| PTU
| EN
| M0
)); /*MMC2_DAT3*/
430 MUX_VAL(CP(MMC2_DAT4
), (IDIS
| PTD
| DIS
| M0
)); /*MMC2_DAT4*/
431 MUX_VAL(CP(MMC2_DAT5
), (IDIS
| PTD
| DIS
| M0
)); /*MMC2_DAT5*/
432 MUX_VAL(CP(MMC2_DAT6
), (IDIS
| PTD
| DIS
| M0
)); /*MMC2_DAT6 */
433 MUX_VAL(CP(MMC2_DAT7
), (IEN
| PTU
| EN
| M0
)); /*MMC2_DAT7*/
435 MUX_VAL(CP(MCBSP3_DX
), (IDIS
| PTD
| DIS
| M0
)); /*McBSP3_DX*/
436 MUX_VAL(CP(MCBSP3_DR
), (IEN
| PTD
| DIS
| M0
)); /*McBSP3_DR*/
437 MUX_VAL(CP(MCBSP3_CLKX
), (IEN
| PTD
| DIS
| M0
)); /*McBSP3_CLKX*/
438 MUX_VAL(CP(MCBSP3_FSX
), (IEN
| PTD
| DIS
| M0
)); /*McBSP3_FSX*/
440 MUX_VAL(CP(UART2_CTS
), (IEN
| PTU
| EN
| M0
)); /*UART2_CTS*/
441 MUX_VAL(CP(UART2_RTS
), (IDIS
| PTD
| DIS
| M0
)); /*UART2_RTS*/
442 MUX_VAL(CP(UART2_TX
), (IDIS
| PTD
| DIS
| M0
)); /*UART2_TX*/
443 MUX_VAL(CP(UART2_RX
), (IEN
| PTD
| DIS
| M0
)); /*UART2_RX*/
445 MUX_VAL(CP(UART1_TX
), (IDIS
| PTD
| DIS
| M0
)); /*UART1_TX*/
446 MUX_VAL(CP(UART1_RTS
), (IDIS
| PTD
| DIS
| M0
)); /*UART1_RTS*/
447 MUX_VAL(CP(UART1_CTS
), (IEN
| PTU
| DIS
| M0
)); /*UART1_CTS*/
448 MUX_VAL(CP(UART1_RX
), (IEN
| PTD
| DIS
| M0
)); /*UART1_RX*/
450 MUX_VAL(CP(MCBSP4_CLKX
), (IDIS
| PTD
| DIS
| M4
)); /*GPIO_152*/
451 MUX_VAL(CP(MCBSP4_DR
), (IDIS
| PTD
| DIS
| M4
)); /*GPIO_153*/
453 MUX_VAL(CP(MCBSP1_CLKR
), (IEN
| PTD
| DIS
| M0
)); /*MCBSP1_CLKR*/
454 MUX_VAL(CP(MCBSP1_FSR
), (IDIS
| PTU
| EN
| M0
)); /*MCBSP1_FSR*/
455 MUX_VAL(CP(MCBSP1_DX
), (IDIS
| PTD
| DIS
| M0
)); /*MCBSP1_DX*/
456 MUX_VAL(CP(MCBSP1_DR
), (IEN
| PTD
| DIS
| M0
)); /*MCBSP1_DR*/
457 MUX_VAL(CP(MCBSP_CLKS
), (IEN
| PTU
| DIS
| M0
)); /*MCBSP_CLKS*/
458 MUX_VAL(CP(MCBSP1_FSX
), (IEN
| PTD
| DIS
| M0
)); /*MCBSP1_FSX*/
459 MUX_VAL(CP(MCBSP1_CLKX
), (IEN
| PTD
| DIS
| M0
)); /*MCBSP1_CLKX*/
461 MUX_VAL(CP(UART3_CTS_RCTX
), (IEN
| PTD
| EN
| M0
)); /*UART3_CTS_*/
462 MUX_VAL(CP(UART3_RTS_SD
), (IDIS
| PTD
| DIS
| M0
)); /*UART3_RTS_SD */
463 MUX_VAL(CP(UART3_RX_IRRX
), (IEN
| PTD
| DIS
| M0
)); /*UART3_RX_IRRX*/
464 MUX_VAL(CP(UART3_TX_IRTX
), (IDIS
| PTD
| DIS
| M0
)); /*UART3_TX_IRTX*/
466 MUX_VAL(CP(HSUSB0_CLK
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_CLK*/
467 MUX_VAL(CP(HSUSB0_STP
), (IDIS
| PTU
| EN
| M0
)); /*HSUSB0_STP*/
468 MUX_VAL(CP(HSUSB0_DIR
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_DIR*/
469 MUX_VAL(CP(HSUSB0_NXT
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_NXT*/
470 MUX_VAL(CP(HSUSB0_DATA0
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_DATA0*/
471 MUX_VAL(CP(HSUSB0_DATA1
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_DATA1*/
472 MUX_VAL(CP(HSUSB0_DATA2
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_DATA2*/
473 MUX_VAL(CP(HSUSB0_DATA3
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_DATA3*/
474 MUX_VAL(CP(HSUSB0_DATA4
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_DATA4*/
475 MUX_VAL(CP(HSUSB0_DATA5
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_DATA5*/
476 MUX_VAL(CP(HSUSB0_DATA6
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_DATA6*/
477 MUX_VAL(CP(HSUSB0_DATA7
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_DATA7*/
479 MUX_VAL(CP(I2C1_SCL
), (IEN
| PTU
| EN
| M0
)); /*I2C1_SCL*/
480 MUX_VAL(CP(I2C1_SDA
), (IEN
| PTU
| EN
| M0
)); /*I2C1_SDA*/
482 MUX_VAL(CP(I2C2_SCL
), (IEN
| PTU
| EN
| M0
)); /*I2C2_SCL*/
483 MUX_VAL(CP(I2C2_SDA
), (IEN
| PTU
| EN
| M0
)); /*I2C2_SDA*/
485 MUX_VAL(CP(I2C3_SCL
), (IEN
| PTU
| EN
| M0
)); /*I2C3_SCL*/
486 MUX_VAL(CP(I2C3_SDA
), (IEN
| PTU
| EN
| M0
)); /*I2C3_SDA*/
488 MUX_VAL(CP(I2C4_SCL
), (IEN
| PTU
| EN
| M0
)); /*I2C4_SCL*/
489 MUX_VAL(CP(I2C4_SDA
), (IEN
| PTU
| EN
| M0
)); /*I2C4_SDA*/
491 MUX_VAL(CP(HDQ_SIO
), (IEN
| PTU
| EN
| M0
)); /*HDQ_SIO*/
493 MUX_VAL(CP(MCSPI1_CLK
), (IEN
| PTD
| DIS
| M0
)); /*McSPI1_CLK*/
494 MUX_VAL(CP(MCSPI1_SIMO
), (IEN
| PTD
| DIS
| M0
)); /*McSPI1_SIMO */
495 MUX_VAL(CP(MCSPI1_SOMI
), (IEN
| PTD
| DIS
| M0
)); /*McSPI1_SOMI */
496 MUX_VAL(CP(MCSPI1_CS0
), (IEN
| PTD
| EN
| M0
)); /*McSPI1_CS0*/
497 MUX_VAL(CP(MCSPI1_CS1
), (IEN
| PTD
| EN
| M4
)); /*GPIO_175*/
498 MUX_VAL(CP(MCSPI1_CS2
), (IEN
| PTU
| DIS
| M4
)); /*GPIO_176*/
499 MUX_VAL(CP(MCSPI1_CS3
), (IEN
| PTD
| EN
| M0
)); /*McSPI1_CS3*/
501 MUX_VAL(CP(MCSPI2_CLK
), (IEN
| PTD
| DIS
| M0
)); /*McSPI2_CLK*/
502 MUX_VAL(CP(MCSPI2_SIMO
), (IEN
| PTD
| DIS
| M0
)); /*McSPI2_SIMO*/
503 MUX_VAL(CP(MCSPI2_SOMI
), (IEN
| PTD
| DIS
| M0
)); /*McSPI2_SOMI*/
504 MUX_VAL(CP(MCSPI2_CS0
), (IEN
| PTD
| EN
| M0
)); /*McSPI2_CS0*/
505 MUX_VAL(CP(MCSPI2_CS1
), (IEN
| PTD
| EN
| M0
)); /*McSPI2_CS1*/
507 MUX_VAL(CP(SYS_32K
), (IEN
| PTD
| DIS
| M0
)); /*SYS_32K*/
508 MUX_VAL(CP(SYS_CLKREQ
), (IEN
| PTD
| DIS
| M0
)); /*SYS_CLKREQ*/
509 MUX_VAL(CP(SYS_NIRQ
), (IEN
| PTU
| EN
| M0
)); /*SYS_nIRQ*/
510 MUX_VAL(CP(SYS_BOOT0
), (IEN
| PTD
| DIS
| M4
)); /*GPIO_2*/
511 MUX_VAL(CP(SYS_BOOT1
), (IEN
| PTD
| DIS
| M4
)); /*GPIO_3 */
512 MUX_VAL(CP(SYS_BOOT2
), (IEN
| PTD
| DIS
| M4
)); /*GPIO_4*/
513 MUX_VAL(CP(SYS_BOOT3
), (IEN
| PTD
| DIS
| M4
)); /*GPIO_5*/
514 MUX_VAL(CP(SYS_BOOT4
), (IEN
| PTD
| DIS
| M4
)); /*GPIO_6*/
515 MUX_VAL(CP(SYS_BOOT5
), (IEN
| PTD
| DIS
| M4
)); /*GPIO_7*/
517 MUX_VAL(CP(SYS_OFF_MODE
), (IEN
| PTD
| DIS
| M0
)); /*SYS_OFF_MODE*/
518 MUX_VAL(CP(SYS_CLKOUT1
), (IEN
| PTD
| DIS
| M0
)); /*SYS_CLKOUT1*/
519 MUX_VAL(CP(SYS_CLKOUT2
), (IEN
| PTU
| EN
| M0
)); /*SYS_CLKOUT2*/
521 MUX_VAL(CP(JTAG_TCK
), (IEN
| PTD
| DIS
| M0
)); /*JTAG_TCK*/
522 MUX_VAL(CP(JTAG_TMS
), (IEN
| PTD
| DIS
| M0
)); /*JTAG_TMS*/
523 MUX_VAL(CP(JTAG_TDI
), (IEN
| PTD
| DIS
| M0
)); /*JTAG_TDI*/
524 MUX_VAL(CP(JTAG_EMU0
), (IEN
| PTD
| DIS
| M0
)); /*JTAG_EMU0*/
525 MUX_VAL(CP(JTAG_EMU1
), (IEN
| PTD
| DIS
| M0
)); /*JTAG_EMU1*/
527 MUX_VAL(CP(ETK_CLK_ES2
), (IDIS
| PTU
| EN
| M0
)); /*ETK_CLK*/
528 MUX_VAL(CP(ETK_CTL_ES2
), (IDIS
| PTD
| DIS
| M0
)); /*ETK_CTL*/
529 MUX_VAL(CP(ETK_D0_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D0*/
530 MUX_VAL(CP(ETK_D1_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D1*/
531 MUX_VAL(CP(ETK_D2_ES2
), (IEN
| PTD
| EN
| M0
)); /*ETK_D2*/
532 MUX_VAL(CP(ETK_D3_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D3*/
533 MUX_VAL(CP(ETK_D4_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D4*/
534 MUX_VAL(CP(ETK_D5_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D5*/
535 MUX_VAL(CP(ETK_D6_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D6*/
536 MUX_VAL(CP(ETK_D7_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D7*/
537 MUX_VAL(CP(ETK_D8_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D8*/
538 MUX_VAL(CP(ETK_D9_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D9*/
539 MUX_VAL(CP(ETK_D10_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D10*/
540 MUX_VAL(CP(ETK_D11_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D11*/
541 MUX_VAL(CP(ETK_D12_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D12*/
542 MUX_VAL(CP(ETK_D13_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D13*/
543 MUX_VAL(CP(ETK_D14_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D14*/
544 MUX_VAL(CP(ETK_D15_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D15*/
546 MUX_VAL(CP(D2D_MCAD1
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad1*/
547 MUX_VAL(CP(D2D_MCAD2
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad2*/
548 MUX_VAL(CP(D2D_MCAD3
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad3*/
549 MUX_VAL(CP(D2D_MCAD4
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad4*/
550 MUX_VAL(CP(D2D_MCAD5
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad5*/
551 MUX_VAL(CP(D2D_MCAD6
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad6*/
552 MUX_VAL(CP(D2D_MCAD7
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad7*/
553 MUX_VAL(CP(D2D_MCAD8
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad8*/
554 MUX_VAL(CP(D2D_MCAD9
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad9*/
555 MUX_VAL(CP(D2D_MCAD10
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad10*/
556 MUX_VAL(CP(D2D_MCAD11
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad11*/
557 MUX_VAL(CP(D2D_MCAD12
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad12*/
558 MUX_VAL(CP(D2D_MCAD13
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad13*/
559 MUX_VAL(CP(D2D_MCAD14
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad14*/
560 MUX_VAL(CP(D2D_MCAD15
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad15*/
561 MUX_VAL(CP(D2D_MCAD16
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad16*/
562 MUX_VAL(CP(D2D_MCAD17
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad17*/
563 MUX_VAL(CP(D2D_MCAD18
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad18*/
564 MUX_VAL(CP(D2D_MCAD19
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad19*/
565 MUX_VAL(CP(D2D_MCAD20
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad20*/
566 MUX_VAL(CP(D2D_MCAD21
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad21*/
567 MUX_VAL(CP(D2D_MCAD22
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad22*/
568 MUX_VAL(CP(D2D_MCAD23
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad23*/
569 MUX_VAL(CP(D2D_MCAD24
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad24*/
570 MUX_VAL(CP(D2D_MCAD25
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad25*/
571 MUX_VAL(CP(D2D_MCAD26
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad26*/
572 MUX_VAL(CP(D2D_MCAD27
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad27*/
573 MUX_VAL(CP(D2D_MCAD28
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad28*/
574 MUX_VAL(CP(D2D_MCAD29
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad29*/
575 MUX_VAL(CP(D2D_MCAD30
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad30*/
576 MUX_VAL(CP(D2D_MCAD31
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad31*/
577 MUX_VAL(CP(D2D_MCAD32
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad32*/
578 MUX_VAL(CP(D2D_MCAD33
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad33*/
579 MUX_VAL(CP(D2D_MCAD34
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad34*/
580 MUX_VAL(CP(D2D_MCAD35
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad35*/
581 MUX_VAL(CP(D2D_MCAD36
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad36*/
582 MUX_VAL(CP(D2D_CLK26MI
), (IEN
| PTD
| DIS
| M0
)); /*d2d_clk26mi*/
583 MUX_VAL(CP(D2D_NRESPWRON
), (IEN
| PTD
| EN
| M0
)); /*d2d_nrespwron*/
584 MUX_VAL(CP(D2D_NRESWARM
), (IEN
| PTU
| EN
| M0
)); /*d2d_nreswarm */
585 MUX_VAL(CP(D2D_ARM9NIRQ
), (IEN
| PTD
| DIS
| M0
)); /*d2d_arm9nirq */
586 MUX_VAL(CP(D2D_UMA2P6FIQ
), (IEN
| PTD
| DIS
| M0
)); /*d2d_uma2p6fiq*/
587 MUX_VAL(CP(D2D_SPINT
), (IEN
| PTD
| EN
| M0
)); /*d2d_spint*/
588 MUX_VAL(CP(D2D_FRINT
), (IEN
| PTD
| EN
| M0
)); /*d2d_frint*/
589 MUX_VAL(CP(D2D_DMAREQ0
), (IEN
| PTD
| DIS
| M0
)); /*d2d_dmareq0*/
590 MUX_VAL(CP(D2D_DMAREQ1
), (IEN
| PTD
| DIS
| M0
)); /*d2d_dmareq1*/
591 MUX_VAL(CP(D2D_DMAREQ2
), (IEN
| PTD
| DIS
| M0
)); /*d2d_dmareq2*/
592 MUX_VAL(CP(D2D_DMAREQ3
), (IEN
| PTD
| DIS
| M0
)); /*d2d_dmareq3*/
593 MUX_VAL(CP(D2D_N3GTRST
), (IEN
| PTD
| DIS
| M0
)); /*d2d_n3gtrst*/
594 MUX_VAL(CP(D2D_N3GTDI
), (IEN
| PTD
| DIS
| M0
)); /*d2d_n3gtdi*/
595 MUX_VAL(CP(D2D_N3GTDO
), (IEN
| PTD
| DIS
| M0
)); /*d2d_n3gtdo*/
596 MUX_VAL(CP(D2D_N3GTMS
), (IEN
| PTD
| DIS
| M0
)); /*d2d_n3gtms*/
597 MUX_VAL(CP(D2D_N3GTCK
), (IEN
| PTD
| DIS
| M0
)); /*d2d_n3gtck*/
598 MUX_VAL(CP(D2D_N3GRTCK
), (IEN
| PTD
| DIS
| M0
)); /*d2d_n3grtck*/
599 MUX_VAL(CP(D2D_MSTDBY
), (IEN
| PTU
| EN
| M0
)); /*d2d_mstdby*/
600 MUX_VAL(CP(D2D_SWAKEUP
), (IEN
| PTD
| EN
| M0
)); /*d2d_swakeup*/
601 MUX_VAL(CP(D2D_IDLEREQ
), (IEN
| PTD
| DIS
| M0
)); /*d2d_idlereq*/
602 MUX_VAL(CP(D2D_IDLEACK
), (IEN
| PTU
| EN
| M0
)); /*d2d_idleack*/
603 MUX_VAL(CP(D2D_MWRITE
), (IEN
| PTD
| DIS
| M0
)); /*d2d_mwrite*/
604 MUX_VAL(CP(D2D_SWRITE
), (IEN
| PTD
| DIS
| M0
)); /*d2d_swrite*/
605 MUX_VAL(CP(D2D_MREAD
), (IEN
| PTD
| DIS
| M0
)); /*d2d_mread*/
606 MUX_VAL(CP(D2D_SREAD
), (IEN
| PTD
| DIS
| M0
)); /*d2d_sread*/
607 MUX_VAL(CP(D2D_MBUSFLAG
), (IEN
| PTD
| DIS
| M0
)); /*d2d_mbusflag*/
608 MUX_VAL(CP(D2D_SBUSFLAG
), (IEN
| PTD
| DIS
| M0
)); /*d2d_sbusflag*/