3 * Logic Product Development <www.logicpd.com>
6 * Peter Barada <peter.barada@logicpd.com>
8 * Derived from Beagle Board and 3430 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * SPDX-License-Identifier: GPL-2.0+
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/mux.h>
25 #include <asm/arch/mem.h>
26 #include <asm/arch/sys_proto.h>
28 #include <asm/mach-types.h>
29 #include <linux/mtd/nand.h>
30 #include <asm/omap_musb.h>
31 #include <linux/errno.h>
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
34 #include <linux/usb/musb.h>
35 #include "omap3logic.h"
37 DECLARE_GLOBAL_DATA_PTR
;
39 /* This is only needed until SPL gets OF support */
40 #ifdef CONFIG_SPL_BUILD
41 static const struct ns16550_platdata omap3logic_serial
= {
42 .base
= OMAP34XX_UART1
,
44 .clock
= V_NS16550_CLK
,
45 .fcr
= UART_FCR_DEFVAL
,
48 U_BOOT_DEVICE(omap3logic_uart
) = {
55 * two dimensional array of strucures containining board name and Linux
56 * machine IDs; row it selected based on CPU column is slected based
57 * on hsusb0_data5 pin having a pulldown resistor
59 static struct board_id
{
66 .name
= "OMAP35xx SOM LV",
67 .machine_id
= MACH_TYPE_OMAP3530_LV_SOM
,
68 .fdtfile
= "logicpd-som-lv-35xx-devkit.dtb",
71 .name
= "OMAP35xx Torpedo",
72 .machine_id
= MACH_TYPE_OMAP3_TORPEDO
,
73 .fdtfile
= "logicpd-torpedo-35xx-devkit.dtb",
78 .name
= "DM37xx SOM LV",
79 .fdtfile
= "logicpd-som-lv-37xx-devkit.dtb",
82 .name
= "DM37xx Torpedo",
83 .fdtfile
= "logicpd-torpedo-37xx-devkit.dtb",
88 #ifdef CONFIG_SPL_OS_BOOT
89 int spl_start_uboot(void)
91 /* break into full u-boot on 'c' */
92 return serial_tstc() && serial_getc() == 'c';
96 #if defined(CONFIG_SPL_BUILD)
98 * Routine: get_board_mem_timings
99 * Description: If we use SPL then there is no x-loader nor config header
100 * so we have to setup the DDR timings ourself on the first bank. This
101 * provides the timing values back to the function that configures
104 void get_board_mem_timings(struct board_sdrc_timings
*timings
)
106 timings
->mr
= MICRON_V_MR_165
;
108 timings
->mcfg
= MICRON_V_MCFG_200(256 << 20);
109 timings
->ctrla
= MICRON_V_ACTIMA_200
;
110 timings
->ctrlb
= MICRON_V_ACTIMB_200
;
111 timings
->rfr_ctrl
= SDP_3430_SDRC_RFR_CTRL_200MHz
;
115 #ifdef CONFIG_USB_MUSB_OMAP2PLUS
116 static struct musb_hdrc_config musb_config
= {
123 static struct omap_musb_board_data musb_board_data
= {
124 .interface_type
= MUSB_INTERFACE_ULPI
,
127 static struct musb_hdrc_platform_data musb_plat
= {
128 #if defined(CONFIG_USB_MUSB_HOST)
130 #elif defined(CONFIG_USB_MUSB_GADGET)
131 .mode
= MUSB_PERIPHERAL
,
133 #error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
135 .config
= &musb_config
,
137 .platform_ops
= &omap2430_ops
,
138 .board_data
= &musb_board_data
,
144 * Routine: misc_init_r
145 * Description: Configure board specific parts
147 int misc_init_r(void)
149 twl4030_power_init();
150 omap_die_id_display();
152 #ifdef CONFIG_USB_MUSB_OMAP2PLUS
153 musb_register(&musb_plat
, &musb_board_data
, (void *)MUSB_BASE
);
160 * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
162 #define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */
165 * Routine: board_init
166 * Description: Early hardware init.
170 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
172 /* boot param addr */
173 gd
->bd
->bi_boot_params
= (OMAP34XX_SDRC_CS0
+ 0x100);
178 #ifdef CONFIG_BOARD_LATE_INIT
179 int board_late_init(void)
181 struct board_id
*board
;
185 * To identify between a SOM LV and Torpedo module,
186 * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
187 * Drive the pin (and let it soak), then read it back.
188 * If the pin is still high its a Torpedo. If low its a SOM LV
191 /* Mux hsusb0_data5 as a GPIO */
192 MUX_VAL(CP(HSUSB0_DATA5
), (IEN
| PTD
| DIS
| M4
));
194 if (gpio_request(BOARD_ID_GPIO
, "husb0_data5.gpio_189") == 0) {
197 * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV
198 * will drain the voltage.
200 gpio_direction_output(BOARD_ID_GPIO
, 0);
201 gpio_set_value(BOARD_ID_GPIO
, 1);
203 /* Let it soak for a bit */
207 * Read state of BOARD_ID_GPIO as an input and if its set.
208 * If so the board is a Torpedo
210 gpio_direction_input(BOARD_ID_GPIO
);
211 val
= gpio_get_value(BOARD_ID_GPIO
);
212 gpio_free(BOARD_ID_GPIO
);
214 board
= &boards
[!!(get_cpu_family() == CPU_OMAP36XX
)][!!val
];
215 printf("Board: %s\n", board
->name
);
217 /* Set the machine_id passed to Linux */
218 if (board
->machine_id
)
219 gd
->bd
->bi_arch_number
= board
->machine_id
;
221 /* If the user has not set fdtimage, set the default */
222 if (!getenv("fdtimage"))
223 setenv("fdtimage", board
->fdtfile
);
226 /* restore hsusb0_data5 pin as hsusb0_data5 */
227 MUX_VAL(CP(HSUSB0_DATA5
), (IEN
| PTD
| DIS
| M0
));
232 #if defined(CONFIG_GENERIC_MMC)
233 int board_mmc_init(bd_t
*bis
)
235 return omap_mmc_init(0, 0, 0, -1, -1);
239 #if defined(CONFIG_GENERIC_MMC)
240 void board_mmc_power_init(void)
242 twl4030_power_mmc_init(0);
246 #ifdef CONFIG_SMC911X
247 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
248 static const u32 gpmc_lan92xx_config
[] = {
249 NET_LAN92XX_GPMC_CONFIG1
,
250 NET_LAN92XX_GPMC_CONFIG2
,
251 NET_LAN92XX_GPMC_CONFIG3
,
252 NET_LAN92XX_GPMC_CONFIG4
,
253 NET_LAN92XX_GPMC_CONFIG5
,
254 NET_LAN92XX_GPMC_CONFIG6
,
257 int board_eth_init(bd_t
*bis
)
259 enable_gpmc_cs_config(gpmc_lan92xx_config
, &gpmc_cfg
->cs
[1],
260 CONFIG_SMC911X_BASE
, GPMC_SIZE_16M
);
262 return smc911x_initialize(0, CONFIG_SMC911X_BASE
);
268 * IDIS - Input Disable
269 * PTD - Pull type Down
271 * DIS - Pull type selection is inactive
272 * EN - Pull type selection is active
274 * The commented string gives the final mux configuration for that pin
278 * Routine: set_muxconf_regs
279 * Description: Setting up the configuration Mux registers specific to the
280 * hardware. Many pins need to be moved from protect to primary
283 void set_muxconf_regs(void)
285 MUX_VAL(CP(SDRC_D0
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D0*/
286 MUX_VAL(CP(SDRC_D1
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D1*/
287 MUX_VAL(CP(SDRC_D2
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D2*/
288 MUX_VAL(CP(SDRC_D3
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D3*/
289 MUX_VAL(CP(SDRC_D4
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D4*/
290 MUX_VAL(CP(SDRC_D5
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D5*/
291 MUX_VAL(CP(SDRC_D6
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D6*/
292 MUX_VAL(CP(SDRC_D7
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D7*/
293 MUX_VAL(CP(SDRC_D8
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D8*/
294 MUX_VAL(CP(SDRC_D9
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D9*/
295 MUX_VAL(CP(SDRC_D10
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D10*/
296 MUX_VAL(CP(SDRC_D11
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D11*/
297 MUX_VAL(CP(SDRC_D12
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D12*/
298 MUX_VAL(CP(SDRC_D13
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D13*/
299 MUX_VAL(CP(SDRC_D14
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D14*/
300 MUX_VAL(CP(SDRC_D15
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D15*/
301 MUX_VAL(CP(SDRC_D16
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D16*/
302 MUX_VAL(CP(SDRC_D17
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D17*/
303 MUX_VAL(CP(SDRC_D18
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D18*/
304 MUX_VAL(CP(SDRC_D19
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D19*/
305 MUX_VAL(CP(SDRC_D20
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D20*/
306 MUX_VAL(CP(SDRC_D21
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D21*/
307 MUX_VAL(CP(SDRC_D22
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D22*/
308 MUX_VAL(CP(SDRC_D23
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D23*/
309 MUX_VAL(CP(SDRC_D24
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D24*/
310 MUX_VAL(CP(SDRC_D25
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D25*/
311 MUX_VAL(CP(SDRC_D26
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D26*/
312 MUX_VAL(CP(SDRC_D27
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D27*/
313 MUX_VAL(CP(SDRC_D28
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D28*/
314 MUX_VAL(CP(SDRC_D29
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D29*/
315 MUX_VAL(CP(SDRC_D30
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D30*/
316 MUX_VAL(CP(SDRC_D31
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_D31*/
317 MUX_VAL(CP(SDRC_CLK
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_CLK*/
318 MUX_VAL(CP(SDRC_DQS0
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_DQS0*/
319 MUX_VAL(CP(SDRC_DQS1
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_DQS1*/
320 MUX_VAL(CP(SDRC_DQS2
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_DQS2*/
321 MUX_VAL(CP(SDRC_DQS3
), (IEN
| PTD
| DIS
| M0
)); /*SDRC_DQS3*/
322 MUX_VAL(CP(SDRC_CKE0
), (IDIS
| PTU
| EN
| M0
)); /*SDRC_CKE0*/
323 MUX_VAL(CP(SDRC_CKE1
), (IDIS
| PTD
| DIS
| M7
)); /*SDRC_CKE1*/
325 MUX_VAL(CP(GPMC_A1
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A1*/
326 MUX_VAL(CP(GPMC_A2
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A2*/
327 MUX_VAL(CP(GPMC_A3
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A3*/
328 MUX_VAL(CP(GPMC_A4
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A4*/
329 MUX_VAL(CP(GPMC_A5
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A5*/
330 MUX_VAL(CP(GPMC_A6
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A6*/
331 MUX_VAL(CP(GPMC_A7
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A7*/
332 MUX_VAL(CP(GPMC_A8
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A8*/
333 MUX_VAL(CP(GPMC_A9
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A9*/
334 MUX_VAL(CP(GPMC_A10
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_A10*/
335 MUX_VAL(CP(GPMC_D0
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D0*/
336 MUX_VAL(CP(GPMC_D1
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D1*/
337 MUX_VAL(CP(GPMC_D2
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D2*/
338 MUX_VAL(CP(GPMC_D3
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D3*/
339 MUX_VAL(CP(GPMC_D4
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D4*/
340 MUX_VAL(CP(GPMC_D5
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D5*/
341 MUX_VAL(CP(GPMC_D6
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D6*/
342 MUX_VAL(CP(GPMC_D7
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D7*/
343 MUX_VAL(CP(GPMC_D8
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D8*/
344 MUX_VAL(CP(GPMC_D9
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D9*/
345 MUX_VAL(CP(GPMC_D10
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D10*/
346 MUX_VAL(CP(GPMC_D11
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D11*/
347 MUX_VAL(CP(GPMC_D12
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D12*/
348 MUX_VAL(CP(GPMC_D13
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D13*/
349 MUX_VAL(CP(GPMC_D14
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D14*/
350 MUX_VAL(CP(GPMC_D15
), (IEN
| PTU
| EN
| M0
)); /*GPMC_D15*/
351 MUX_VAL(CP(GPMC_NCS0
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_nCS0*/
352 MUX_VAL(CP(GPMC_NCS1
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_nCS1*/
353 MUX_VAL(CP(GPMC_NCS2
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_nCS2*/
354 MUX_VAL(CP(GPMC_NCS3
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_nCS3*/
355 MUX_VAL(CP(GPMC_NCS4
), (IEN
| PTU
| EN
| M0
)); /*GPMC_nCS4*/
356 MUX_VAL(CP(GPMC_NCS5
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_nCS5*/
357 MUX_VAL(CP(GPMC_NCS6
), (IEN
| PTU
| EN
| M0
)); /*GPMC_nCS6*/
358 MUX_VAL(CP(GPMC_NCS7
), (IEN
| PTU
| EN
| M0
)); /*GPMC_nCS7*/
359 MUX_VAL(CP(GPMC_CLK
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_CLK*/
360 MUX_VAL(CP(GPMC_NADV_ALE
), (IDIS
| PTD
| DIS
| M0
)); /*GPMC_nADV_ALE*/
361 MUX_VAL(CP(GPMC_NOE
), (IDIS
| PTD
| DIS
| M0
)); /*GPMC_nOE*/
362 MUX_VAL(CP(GPMC_NWE
), (IDIS
| PTD
| DIS
| M0
)); /*GPMC_nWE*/
363 MUX_VAL(CP(GPMC_NBE0_CLE
), (IDIS
| PTU
| EN
| M0
)); /*GPMC_nBE0_CLE*/
364 MUX_VAL(CP(GPMC_NBE1
), (IEN
| PTU
| EN
| M0
)); /*GPMC_nBE1*/
365 MUX_VAL(CP(GPMC_NWP
), (IEN
| PTD
| DIS
| M0
)); /*GPMC_nWP*/
366 MUX_VAL(CP(GPMC_WAIT0
), (IEN
| PTU
| EN
| M0
)); /*GPMC_WAIT0*/
367 MUX_VAL(CP(GPMC_WAIT1
), (IEN
| PTU
| EN
| M0
)); /*GPMC_WAIT1*/
368 MUX_VAL(CP(GPMC_WAIT2
), (IEN
| PTU
| EN
| M4
)); /*GPIO_64*/
369 MUX_VAL(CP(GPMC_WAIT3
), (IEN
| PTU
| EN
| M0
)); /*GPMC_WAIT3*/
371 MUX_VAL(CP(CAM_HS
), (IEN
| PTU
| EN
| M0
)); /*CAM_HS */
372 MUX_VAL(CP(CAM_VS
), (IEN
| PTU
| EN
| M0
)); /*CAM_VS */
373 MUX_VAL(CP(CAM_XCLKA
), (IDIS
| PTD
| DIS
| M0
)); /*CAM_XCLKA*/
374 MUX_VAL(CP(CAM_PCLK
), (IEN
| PTU
| EN
| M0
)); /*CAM_PCLK*/
375 MUX_VAL(CP(CAM_FLD
), (IDIS
| PTD
| DIS
| M4
)); /*GPIO_98*/
376 MUX_VAL(CP(CAM_D0
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D0*/
377 MUX_VAL(CP(CAM_D1
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D1*/
378 MUX_VAL(CP(CAM_D2
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D2*/
379 MUX_VAL(CP(CAM_D3
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D3*/
380 MUX_VAL(CP(CAM_D4
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D4*/
381 MUX_VAL(CP(CAM_D5
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D5*/
382 MUX_VAL(CP(CAM_D6
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D6*/
383 MUX_VAL(CP(CAM_D7
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D7*/
384 MUX_VAL(CP(CAM_D8
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D8*/
385 MUX_VAL(CP(CAM_D9
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D9*/
386 MUX_VAL(CP(CAM_D10
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D10*/
387 MUX_VAL(CP(CAM_D11
), (IEN
| PTD
| DIS
| M0
)); /*CAM_D11*/
388 MUX_VAL(CP(CAM_XCLKB
), (IDIS
| PTD
| DIS
| M0
)); /*CAM_XCLKB*/
389 MUX_VAL(CP(CAM_WEN
), (IEN
| PTD
| DIS
| M4
)); /*GPIO_167*/
390 MUX_VAL(CP(CAM_STROBE
), (IDIS
| PTD
| DIS
| M0
)); /*CAM_STROBE*/
392 MUX_VAL(CP(CSI2_DX0
), (IEN
| PTD
| DIS
| M0
)); /*CSI2_DX0*/
393 MUX_VAL(CP(CSI2_DY0
), (IEN
| PTD
| DIS
| M0
)); /*CSI2_DY0*/
394 MUX_VAL(CP(CSI2_DX1
), (IEN
| PTD
| DIS
| M0
)); /*CSI2_DX1*/
395 MUX_VAL(CP(CSI2_DY1
), (IEN
| PTD
| DIS
| M0
)); /*CSI2_DY1*/
397 MUX_VAL(CP(MCBSP2_FSX
), (IEN
| PTD
| DIS
| M0
)); /*McBSP2_FSX*/
398 MUX_VAL(CP(MCBSP2_CLKX
), (IEN
| PTD
| DIS
| M0
)); /*McBSP2_CLKX*/
399 MUX_VAL(CP(MCBSP2_DR
), (IEN
| PTD
| DIS
| M0
)); /*McBSP2_DR*/
400 MUX_VAL(CP(MCBSP2_DX
), (IDIS
| PTD
| DIS
| M0
)); /*McBSP2_DX*/
402 MUX_VAL(CP(MMC1_CLK
), (IDIS
| PTU
| EN
| M0
)); /*MMC1_CLK*/
403 MUX_VAL(CP(MMC1_CMD
), (IEN
| PTU
| EN
| M0
)); /*MMC1_CMD*/
404 MUX_VAL(CP(MMC1_DAT0
), (IEN
| PTU
| EN
| M0
)); /*MMC1_DAT0*/
405 MUX_VAL(CP(MMC1_DAT1
), (IEN
| PTU
| EN
| M0
)); /*MMC1_DAT1*/
406 MUX_VAL(CP(MMC1_DAT2
), (IEN
| PTU
| EN
| M0
)); /*MMC1_DAT2*/
407 MUX_VAL(CP(MMC1_DAT3
), (IEN
| PTU
| EN
| M0
)); /*MMC1_DAT3*/
408 MUX_VAL(CP(MMC1_DAT4
), (IEN
| PTU
| EN
| M0
)); /*MMC1_DAT4*/
409 MUX_VAL(CP(MMC1_DAT5
), (IEN
| PTU
| EN
| M0
)); /*MMC1_DAT5*/
410 MUX_VAL(CP(MMC1_DAT6
), (IEN
| PTU
| EN
| M0
)); /*MMC1_DAT6*/
411 MUX_VAL(CP(MMC1_DAT7
), (IEN
| PTU
| EN
| M0
)); /*MMC1_DAT7*/
413 MUX_VAL(CP(MMC2_CLK
), (IEN
| PTD
| DIS
| M0
)); /*MMC2_CLK*/
414 MUX_VAL(CP(MMC2_CMD
), (IEN
| PTU
| EN
| M0
)); /*MMC2_CMD*/
415 MUX_VAL(CP(MMC2_DAT0
), (IEN
| PTU
| EN
| M0
)); /*MMC2_DAT0*/
416 MUX_VAL(CP(MMC2_DAT1
), (IEN
| PTU
| EN
| M0
)); /*MMC2_DAT1*/
417 MUX_VAL(CP(MMC2_DAT2
), (IEN
| PTU
| EN
| M0
)); /*MMC2_DAT2*/
418 MUX_VAL(CP(MMC2_DAT3
), (IEN
| PTU
| EN
| M0
)); /*MMC2_DAT3*/
419 MUX_VAL(CP(MMC2_DAT4
), (IDIS
| PTD
| DIS
| M0
)); /*MMC2_DAT4*/
420 MUX_VAL(CP(MMC2_DAT5
), (IDIS
| PTD
| DIS
| M0
)); /*MMC2_DAT5*/
421 MUX_VAL(CP(MMC2_DAT6
), (IDIS
| PTD
| DIS
| M0
)); /*MMC2_DAT6 */
422 MUX_VAL(CP(MMC2_DAT7
), (IEN
| PTU
| EN
| M0
)); /*MMC2_DAT7*/
424 MUX_VAL(CP(MCBSP3_DX
), (IDIS
| PTD
| DIS
| M0
)); /*McBSP3_DX*/
425 MUX_VAL(CP(MCBSP3_DR
), (IEN
| PTD
| DIS
| M0
)); /*McBSP3_DR*/
426 MUX_VAL(CP(MCBSP3_CLKX
), (IEN
| PTD
| DIS
| M0
)); /*McBSP3_CLKX*/
427 MUX_VAL(CP(MCBSP3_FSX
), (IEN
| PTD
| DIS
| M0
)); /*McBSP3_FSX*/
429 MUX_VAL(CP(UART2_CTS
), (IEN
| PTU
| EN
| M0
)); /*UART2_CTS*/
430 MUX_VAL(CP(UART2_RTS
), (IDIS
| PTD
| DIS
| M0
)); /*UART2_RTS*/
431 MUX_VAL(CP(UART2_TX
), (IDIS
| PTD
| DIS
| M0
)); /*UART2_TX*/
432 MUX_VAL(CP(UART2_RX
), (IEN
| PTD
| DIS
| M0
)); /*UART2_RX*/
434 MUX_VAL(CP(UART1_TX
), (IDIS
| PTD
| DIS
| M0
)); /*UART1_TX*/
435 MUX_VAL(CP(UART1_RTS
), (IDIS
| PTD
| DIS
| M0
)); /*UART1_RTS*/
436 MUX_VAL(CP(UART1_CTS
), (IEN
| PTU
| DIS
| M0
)); /*UART1_CTS*/
437 MUX_VAL(CP(UART1_RX
), (IEN
| PTD
| DIS
| M0
)); /*UART1_RX*/
439 MUX_VAL(CP(MCBSP4_CLKX
), (IDIS
| PTD
| DIS
| M4
)); /*GPIO_152*/
440 MUX_VAL(CP(MCBSP4_DR
), (IDIS
| PTD
| DIS
| M4
)); /*GPIO_153*/
442 MUX_VAL(CP(MCBSP1_CLKR
), (IEN
| PTD
| DIS
| M0
)); /*MCBSP1_CLKR*/
443 MUX_VAL(CP(MCBSP1_FSR
), (IDIS
| PTU
| EN
| M0
)); /*MCBSP1_FSR*/
444 MUX_VAL(CP(MCBSP1_DX
), (IDIS
| PTD
| DIS
| M0
)); /*MCBSP1_DX*/
445 MUX_VAL(CP(MCBSP1_DR
), (IEN
| PTD
| DIS
| M0
)); /*MCBSP1_DR*/
446 MUX_VAL(CP(MCBSP_CLKS
), (IEN
| PTU
| DIS
| M0
)); /*MCBSP_CLKS*/
447 MUX_VAL(CP(MCBSP1_FSX
), (IEN
| PTD
| DIS
| M0
)); /*MCBSP1_FSX*/
448 MUX_VAL(CP(MCBSP1_CLKX
), (IEN
| PTD
| DIS
| M0
)); /*MCBSP1_CLKX*/
450 MUX_VAL(CP(UART3_CTS_RCTX
), (IEN
| PTD
| EN
| M0
)); /*UART3_CTS_*/
451 MUX_VAL(CP(UART3_RTS_SD
), (IDIS
| PTD
| DIS
| M0
)); /*UART3_RTS_SD */
452 MUX_VAL(CP(UART3_RX_IRRX
), (IEN
| PTD
| DIS
| M0
)); /*UART3_RX_IRRX*/
453 MUX_VAL(CP(UART3_TX_IRTX
), (IDIS
| PTD
| DIS
| M0
)); /*UART3_TX_IRTX*/
455 MUX_VAL(CP(HSUSB0_CLK
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_CLK*/
456 MUX_VAL(CP(HSUSB0_STP
), (IDIS
| PTU
| EN
| M0
)); /*HSUSB0_STP*/
457 MUX_VAL(CP(HSUSB0_DIR
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_DIR*/
458 MUX_VAL(CP(HSUSB0_NXT
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_NXT*/
459 MUX_VAL(CP(HSUSB0_DATA0
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_DATA0*/
460 MUX_VAL(CP(HSUSB0_DATA1
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_DATA1*/
461 MUX_VAL(CP(HSUSB0_DATA2
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_DATA2*/
462 MUX_VAL(CP(HSUSB0_DATA3
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_DATA3*/
463 MUX_VAL(CP(HSUSB0_DATA4
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_DATA4*/
464 MUX_VAL(CP(HSUSB0_DATA5
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_DATA5*/
465 MUX_VAL(CP(HSUSB0_DATA6
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_DATA6*/
466 MUX_VAL(CP(HSUSB0_DATA7
), (IEN
| PTD
| DIS
| M0
)); /*HSUSB0_DATA7*/
468 MUX_VAL(CP(I2C1_SCL
), (IEN
| PTU
| EN
| M0
)); /*I2C1_SCL*/
469 MUX_VAL(CP(I2C1_SDA
), (IEN
| PTU
| EN
| M0
)); /*I2C1_SDA*/
471 MUX_VAL(CP(I2C2_SCL
), (IEN
| PTU
| EN
| M0
)); /*I2C2_SCL*/
472 MUX_VAL(CP(I2C2_SDA
), (IEN
| PTU
| EN
| M0
)); /*I2C2_SDA*/
474 MUX_VAL(CP(I2C3_SCL
), (IEN
| PTU
| EN
| M0
)); /*I2C3_SCL*/
475 MUX_VAL(CP(I2C3_SDA
), (IEN
| PTU
| EN
| M0
)); /*I2C3_SDA*/
477 MUX_VAL(CP(I2C4_SCL
), (IEN
| PTU
| EN
| M0
)); /*I2C4_SCL*/
478 MUX_VAL(CP(I2C4_SDA
), (IEN
| PTU
| EN
| M0
)); /*I2C4_SDA*/
480 MUX_VAL(CP(HDQ_SIO
), (IEN
| PTU
| EN
| M0
)); /*HDQ_SIO*/
482 MUX_VAL(CP(MCSPI1_CLK
), (IEN
| PTD
| DIS
| M0
)); /*McSPI1_CLK*/
483 MUX_VAL(CP(MCSPI1_SIMO
), (IEN
| PTD
| DIS
| M0
)); /*McSPI1_SIMO */
484 MUX_VAL(CP(MCSPI1_SOMI
), (IEN
| PTD
| DIS
| M0
)); /*McSPI1_SOMI */
485 MUX_VAL(CP(MCSPI1_CS0
), (IEN
| PTD
| EN
| M0
)); /*McSPI1_CS0*/
486 MUX_VAL(CP(MCSPI1_CS1
), (IEN
| PTD
| EN
| M4
)); /*GPIO_175*/
487 MUX_VAL(CP(MCSPI1_CS2
), (IEN
| PTU
| DIS
| M4
)); /*GPIO_176*/
488 MUX_VAL(CP(MCSPI1_CS3
), (IEN
| PTD
| EN
| M0
)); /*McSPI1_CS3*/
490 MUX_VAL(CP(MCSPI2_CLK
), (IEN
| PTD
| DIS
| M0
)); /*McSPI2_CLK*/
491 MUX_VAL(CP(MCSPI2_SIMO
), (IEN
| PTD
| DIS
| M0
)); /*McSPI2_SIMO*/
492 MUX_VAL(CP(MCSPI2_SOMI
), (IEN
| PTD
| DIS
| M0
)); /*McSPI2_SOMI*/
493 MUX_VAL(CP(MCSPI2_CS0
), (IEN
| PTD
| EN
| M0
)); /*McSPI2_CS0*/
494 MUX_VAL(CP(MCSPI2_CS1
), (IEN
| PTD
| EN
| M0
)); /*McSPI2_CS1*/
496 MUX_VAL(CP(SYS_32K
), (IEN
| PTD
| DIS
| M0
)); /*SYS_32K*/
497 MUX_VAL(CP(SYS_CLKREQ
), (IEN
| PTD
| DIS
| M0
)); /*SYS_CLKREQ*/
498 MUX_VAL(CP(SYS_NIRQ
), (IEN
| PTU
| EN
| M0
)); /*SYS_nIRQ*/
499 MUX_VAL(CP(SYS_BOOT0
), (IEN
| PTD
| DIS
| M4
)); /*GPIO_2*/
500 MUX_VAL(CP(SYS_BOOT1
), (IEN
| PTD
| DIS
| M4
)); /*GPIO_3 */
501 MUX_VAL(CP(SYS_BOOT2
), (IEN
| PTD
| DIS
| M4
)); /*GPIO_4*/
502 MUX_VAL(CP(SYS_BOOT3
), (IEN
| PTD
| DIS
| M4
)); /*GPIO_5*/
503 MUX_VAL(CP(SYS_BOOT4
), (IEN
| PTD
| DIS
| M4
)); /*GPIO_6*/
504 MUX_VAL(CP(SYS_BOOT5
), (IEN
| PTD
| DIS
| M4
)); /*GPIO_7*/
506 MUX_VAL(CP(SYS_OFF_MODE
), (IEN
| PTD
| DIS
| M0
)); /*SYS_OFF_MODE*/
507 MUX_VAL(CP(SYS_CLKOUT1
), (IEN
| PTD
| DIS
| M0
)); /*SYS_CLKOUT1*/
508 MUX_VAL(CP(SYS_CLKOUT2
), (IEN
| PTU
| EN
| M0
)); /*SYS_CLKOUT2*/
510 MUX_VAL(CP(JTAG_TCK
), (IEN
| PTD
| DIS
| M0
)); /*JTAG_TCK*/
511 MUX_VAL(CP(JTAG_TMS
), (IEN
| PTD
| DIS
| M0
)); /*JTAG_TMS*/
512 MUX_VAL(CP(JTAG_TDI
), (IEN
| PTD
| DIS
| M0
)); /*JTAG_TDI*/
513 MUX_VAL(CP(JTAG_EMU0
), (IEN
| PTD
| DIS
| M0
)); /*JTAG_EMU0*/
514 MUX_VAL(CP(JTAG_EMU1
), (IEN
| PTD
| DIS
| M0
)); /*JTAG_EMU1*/
516 MUX_VAL(CP(ETK_CLK_ES2
), (IDIS
| PTU
| EN
| M0
)); /*ETK_CLK*/
517 MUX_VAL(CP(ETK_CTL_ES2
), (IDIS
| PTD
| DIS
| M0
)); /*ETK_CTL*/
518 MUX_VAL(CP(ETK_D0_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D0*/
519 MUX_VAL(CP(ETK_D1_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D1*/
520 MUX_VAL(CP(ETK_D2_ES2
), (IEN
| PTD
| EN
| M0
)); /*ETK_D2*/
521 MUX_VAL(CP(ETK_D3_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D3*/
522 MUX_VAL(CP(ETK_D4_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D4*/
523 MUX_VAL(CP(ETK_D5_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D5*/
524 MUX_VAL(CP(ETK_D6_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D6*/
525 MUX_VAL(CP(ETK_D7_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D7*/
526 MUX_VAL(CP(ETK_D8_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D8*/
527 MUX_VAL(CP(ETK_D9_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D9*/
528 MUX_VAL(CP(ETK_D10_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D10*/
529 MUX_VAL(CP(ETK_D11_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D11*/
530 MUX_VAL(CP(ETK_D12_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D12*/
531 MUX_VAL(CP(ETK_D13_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D13*/
532 MUX_VAL(CP(ETK_D14_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D14*/
533 MUX_VAL(CP(ETK_D15_ES2
), (IEN
| PTD
| DIS
| M0
)); /*ETK_D15*/
535 MUX_VAL(CP(D2D_MCAD1
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad1*/
536 MUX_VAL(CP(D2D_MCAD2
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad2*/
537 MUX_VAL(CP(D2D_MCAD3
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad3*/
538 MUX_VAL(CP(D2D_MCAD4
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad4*/
539 MUX_VAL(CP(D2D_MCAD5
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad5*/
540 MUX_VAL(CP(D2D_MCAD6
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad6*/
541 MUX_VAL(CP(D2D_MCAD7
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad7*/
542 MUX_VAL(CP(D2D_MCAD8
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad8*/
543 MUX_VAL(CP(D2D_MCAD9
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad9*/
544 MUX_VAL(CP(D2D_MCAD10
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad10*/
545 MUX_VAL(CP(D2D_MCAD11
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad11*/
546 MUX_VAL(CP(D2D_MCAD12
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad12*/
547 MUX_VAL(CP(D2D_MCAD13
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad13*/
548 MUX_VAL(CP(D2D_MCAD14
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad14*/
549 MUX_VAL(CP(D2D_MCAD15
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad15*/
550 MUX_VAL(CP(D2D_MCAD16
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad16*/
551 MUX_VAL(CP(D2D_MCAD17
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad17*/
552 MUX_VAL(CP(D2D_MCAD18
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad18*/
553 MUX_VAL(CP(D2D_MCAD19
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad19*/
554 MUX_VAL(CP(D2D_MCAD20
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad20*/
555 MUX_VAL(CP(D2D_MCAD21
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad21*/
556 MUX_VAL(CP(D2D_MCAD22
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad22*/
557 MUX_VAL(CP(D2D_MCAD23
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad23*/
558 MUX_VAL(CP(D2D_MCAD24
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad24*/
559 MUX_VAL(CP(D2D_MCAD25
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad25*/
560 MUX_VAL(CP(D2D_MCAD26
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad26*/
561 MUX_VAL(CP(D2D_MCAD27
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad27*/
562 MUX_VAL(CP(D2D_MCAD28
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad28*/
563 MUX_VAL(CP(D2D_MCAD29
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad29*/
564 MUX_VAL(CP(D2D_MCAD30
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad30*/
565 MUX_VAL(CP(D2D_MCAD31
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad31*/
566 MUX_VAL(CP(D2D_MCAD32
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad32*/
567 MUX_VAL(CP(D2D_MCAD33
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad33*/
568 MUX_VAL(CP(D2D_MCAD34
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad34*/
569 MUX_VAL(CP(D2D_MCAD35
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad35*/
570 MUX_VAL(CP(D2D_MCAD36
), (IEN
| PTD
| EN
| M0
)); /*d2d_mcad36*/
571 MUX_VAL(CP(D2D_CLK26MI
), (IEN
| PTD
| DIS
| M0
)); /*d2d_clk26mi*/
572 MUX_VAL(CP(D2D_NRESPWRON
), (IEN
| PTD
| EN
| M0
)); /*d2d_nrespwron*/
573 MUX_VAL(CP(D2D_NRESWARM
), (IEN
| PTU
| EN
| M0
)); /*d2d_nreswarm */
574 MUX_VAL(CP(D2D_ARM9NIRQ
), (IEN
| PTD
| DIS
| M0
)); /*d2d_arm9nirq */
575 MUX_VAL(CP(D2D_UMA2P6FIQ
), (IEN
| PTD
| DIS
| M0
)); /*d2d_uma2p6fiq*/
576 MUX_VAL(CP(D2D_SPINT
), (IEN
| PTD
| EN
| M0
)); /*d2d_spint*/
577 MUX_VAL(CP(D2D_FRINT
), (IEN
| PTD
| EN
| M0
)); /*d2d_frint*/
578 MUX_VAL(CP(D2D_DMAREQ0
), (IEN
| PTD
| DIS
| M0
)); /*d2d_dmareq0*/
579 MUX_VAL(CP(D2D_DMAREQ1
), (IEN
| PTD
| DIS
| M0
)); /*d2d_dmareq1*/
580 MUX_VAL(CP(D2D_DMAREQ2
), (IEN
| PTD
| DIS
| M0
)); /*d2d_dmareq2*/
581 MUX_VAL(CP(D2D_DMAREQ3
), (IEN
| PTD
| DIS
| M0
)); /*d2d_dmareq3*/
582 MUX_VAL(CP(D2D_N3GTRST
), (IEN
| PTD
| DIS
| M0
)); /*d2d_n3gtrst*/
583 MUX_VAL(CP(D2D_N3GTDI
), (IEN
| PTD
| DIS
| M0
)); /*d2d_n3gtdi*/
584 MUX_VAL(CP(D2D_N3GTDO
), (IEN
| PTD
| DIS
| M0
)); /*d2d_n3gtdo*/
585 MUX_VAL(CP(D2D_N3GTMS
), (IEN
| PTD
| DIS
| M0
)); /*d2d_n3gtms*/
586 MUX_VAL(CP(D2D_N3GTCK
), (IEN
| PTD
| DIS
| M0
)); /*d2d_n3gtck*/
587 MUX_VAL(CP(D2D_N3GRTCK
), (IEN
| PTD
| DIS
| M0
)); /*d2d_n3grtck*/
588 MUX_VAL(CP(D2D_MSTDBY
), (IEN
| PTU
| EN
| M0
)); /*d2d_mstdby*/
589 MUX_VAL(CP(D2D_SWAKEUP
), (IEN
| PTD
| EN
| M0
)); /*d2d_swakeup*/
590 MUX_VAL(CP(D2D_IDLEREQ
), (IEN
| PTD
| DIS
| M0
)); /*d2d_idlereq*/
591 MUX_VAL(CP(D2D_IDLEACK
), (IEN
| PTU
| EN
| M0
)); /*d2d_idleack*/
592 MUX_VAL(CP(D2D_MWRITE
), (IEN
| PTD
| DIS
| M0
)); /*d2d_mwrite*/
593 MUX_VAL(CP(D2D_SWRITE
), (IEN
| PTD
| DIS
| M0
)); /*d2d_swrite*/
594 MUX_VAL(CP(D2D_MREAD
), (IEN
| PTD
| DIS
| M0
)); /*d2d_mread*/
595 MUX_VAL(CP(D2D_SREAD
), (IEN
| PTD
| DIS
| M0
)); /*d2d_sread*/
596 MUX_VAL(CP(D2D_MBUSFLAG
), (IEN
| PTD
| DIS
| M0
)); /*d2d_mbusflag*/
597 MUX_VAL(CP(D2D_SBUSFLAG
), (IEN
| PTD
| DIS
| M0
)); /*d2d_sbusflag*/