board/lpd7a40x/memsetup.S

   1 /*
   2  * Memory Setup - initialize memory controller(s) for devices required
   3  *                to boot and relocate
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24
  25 #include <config.h>
  26 #include <version.h>
  27
  28
  29 /* memory controller */
  30 #define BCRX_DEFAULT    (0x0000fbe0)
  31 #define BCRX_MW_8       (0x00000000)
  32 #define BCRX_MW_16      (0x10000000)
  33 #define BCRX_MW_32      (0x20000000)
  34 #define BCRX_PME        (0x08000000)
  35 #define BCRX_WP         (0x04000000)
  36 #define BCRX_WST2_SHIFT (11)
  37 #define BCRX_WST1_SHIFT (5)
  38 #define BCRX_IDCY_SHIFT (0)
  39
  40 /* Bank0 Async Flash */
  41 #define BCR0            (0x80002000)
  42 #define BCR0_FLASH      (BCRX_MW_32 | (0x08<<BCRX_WST2_SHIFT) | (0x0E<<BCRX_WST1_SHIFT))
  43
  44 /* Bank1 Open */
  45 #define BCR1    (0x80002004)
  46
  47 /* Bank2 Not used (EEPROM?) */
  48 #define BCR2    (0x80002008)
  49
  50 /* Bank3 Not used */
  51 #define BCR3    (0x8000200C)
  52
  53 /* Bank4 PC Card1 */
  54
  55 /* Bank5 PC Card2 */
  56
  57 /* Bank6 CPLD IO Controller Peripherals (slow) */
  58 #define BCR6            (0x80002018)
  59 #define BCR6_CPLD_SLOW  (BCRX_DEFAULT | BCRX_MW_16)
  60
  61 /* Bank7 CPLD IO Controller Peripherals (fast) */
  62 #define BCR7            (0x8000201C)
  63 #define BCR7_CPLD_FAST  (BCRX_MW_16 | (0x16<<BCRX_WST2_SHIFT) | (0x16<<BCRX_WST1_SHIFT) | (0x2<<BCRX_IDCY_SHIFT))
  64
  65 /* SDRAM */
  66 #define GBLCNFG         (0x80002404)
  67 #define GC_CKE          (0x80000000)
  68 #define GC_CKSD         (0x40000000)
  69 #define GC_LCR          (0x00000040)
  70 #define GC_SMEMBURST    (0x00000020)
  71 #define GC_MRS          (0x00000002)
  72 #define GC_INIT         (0x00000001)
  73
  74 #define GC_CMD_NORMAL           (GC_CKE)
  75 #define GC_CMD_MODE             (GC_CKE | GC_MRS)
  76 #define GC_CMD_SYNCFLASH_LOAD   (GC_CKE | GC_MRS | GC_LCR)
  77 #define GC_CMD_PRECHARGEALL     (GC_CKE | GC_INIT)
  78 #define GC_CMD_NOP              (GC_CKE | GC_INIT | GC_MRS)
  79
  80 #define RFSHTMR         (0x80002408)
  81 #define RFSHTMR_INIT    (10)    /* period=100 ns, HCLK=100Mhz, (2048+1-15.6*66) */
  82 #define RFSHTMR_NORMAL  (1500)  /* period=15.6 us, HCLK=100Mhz, (2048+1-15.6*66) */
  83
  84 #define SDCSCX_BASE             (0x80002410)
  85 #define SDCSCX_DEFAULT          (0x01220008)
  86 #define SDCSCX_AUTOPC           (0x01000000)
  87 #define SDCSCX_RAS2CAS_2        (0x00200000)
  88 #define SDCSCX_RAS2CAS_3        (0x00300000)
  89 #define SDCSCX_WBL              (0x00080000)
  90 #define SDCSCX_CASLAT_8         (0x00070000)
  91 #define SDCSCX_CASLAT_7         (0x00060000)
  92 #define SDCSCX_CASLAT_6         (0x00050000)
  93 #define SDCSCX_CASLAT_5         (0x00040000)
  94 #define SDCSCX_CASLAT_4         (0x00030000)
  95 #define SDCSCX_CASLAT_3         (0x00020000)
  96 #define SDCSCX_CASLAT_2         (0x00010000)
  97 #define SDCSCX_2KPAGE           (0x00000040)
  98 #define SDCSCX_SROMLL           (0x00000020)
  99 #define SDCSCX_SROM512          (0x00000010)
 100 #define SDCSCX_4BNK             (0x00000008)
 101 #define SDCSCX_2BNK             (0x00000000)
 102 #define SDCSCX_EBW_16           (0x00000004)
 103 #define SDCSCX_EBW_32           (0x00000000)
 104
 105 #define SDRAM_BASE              (0xC0000000)
 106 #define SDCSC_BANK_OFFSET       (0x10000000)
 107
 108 /*
 109  * The SDRAM DEVICE MODE PROGRAMMING VALUE
 110  */
 111 #define BURST_LENGTH_4          (0x010 << 10)
 112 #define BURST_LENGTH_8          (0x011 << 10)
 113 #define WBURST_LENGTH_BL        (0x01 << 19)
 114 #define WBURST_LENGTH_SINGLE    (0x01 << 19)
 115 #define CAS_2                   (0x010 << 14)
 116 #define CAS_3                   (0x011 << 14)
 117 #define BAT_SEQUENTIAL          (0 << 13)
 118 #define BAT_INTERLEAVED         (1 << 13)
 119 #define OPM_NORMAL              (0x00 << 17)
 120 #define SDRAM_DEVICE_MODE       (WBURST_LENGTH_BL|OPM_NORMAL|CAS_3|BAT_SEQUENTIAL|BURST_LENGTH_4)
 121
 122
 123 #define TIMER1_BASE     (0x80000C00)
 124
 125 /*
 126  * special lookup flags
 127  */
 128 #define DO_MEM_DELAY    1
 129 #define DO_MEM_READ     2
 130
 131 _TEXT_BASE:
 132         .word   TEXT_BASE
 133
 134 .globl memsetup
 135 memsetup:
 136         mov     r9, lr  @ save return address
 137
 138         /* memory control configuration */
 139         /* make r0 relative the current location so that it */
 140         /* reads INITMEM_DATA out of FLASH rather than memory ! */
 141         /*   r0 = current word pointer */
 142         /*   r1 = end word location, one word past last actual word */
 143         /*   r3 = address for writes, special lookup flags */
 144         /*   r4 = value for writes, delay constants, or read addresses */
 145         /*   r2 = location for mem reads */
 146
 147         ldr     r0, =INITMEM_DATA
 148         ldr     r1, _TEXT_BASE
 149         sub     r0, r0, r1
 150         add     r1, r0, #112
 151
 152 mem_loop:
 153         cmp     r1, r0
 154         moveq   pc, r9          @ Done
 155
 156         ldr     r3, [r0], #4    @ Fetch Destination Register Address, or 1 for delay
 157         ldr     r4, [r0], #4    @ value
 158
 159         cmp     r3, #DO_MEM_DELAY
 160         bleq    mem_delay
 161         beq     mem_loop
 162         cmp     r3, #DO_MEM_READ
 163         ldreq   r2, [r4]
 164         beq     mem_loop
 165         str     r4, [r3]        @ normal register/ram store
 166         b       mem_loop
 167
 168 mem_delay:
 169         ldr     r5, =TIMER1_BASE
 170         mov     r6, r4, LSR #1  @ timer resolution is ~2us
 171         str     r6, [r5]
 172         mov     r6, #0x88       @ using 508.469KHz clock, enable
 173         str     r6, [r5, #8]
 174 0:      ldr     r6, [r5, #4]    @ timer value
 175         cmp     r6, #0
 176         bne     0b
 177         mov     r6, #0          @ disable timer
 178         str     r6, [r5, #8]
 179         mov     pc, lr
 180
 181         .ltorg
 182 /* the literal pools origin */
 183
 184 INITMEM_DATA:
 185         .word   BCR0
 186         .word   BCR0_FLASH
 187         .word   BCR6
 188         .word   BCR6_CPLD_SLOW
 189         .word   BCR7
 190         .word   BCR7_CPLD_FAST
 191         .word   SDCSCX_BASE
 192         .word   (SDCSCX_RAS2CAS_3 | SDCSCX_CASLAT_3 | SDCSCX_SROMLL | SDCSCX_4BNK | SDCSCX_EBW_32)
 193         .word   GBLCNFG
 194         .word   GC_CMD_NOP
 195         .word   DO_MEM_DELAY
 196         .word   200
 197         .word   GBLCNFG
 198         .word   GC_CMD_PRECHARGEALL
 199         .word   RFSHTMR
 200         .word   RFSHTMR_INIT
 201         .word   DO_MEM_DELAY
 202         .word   8
 203         .word   RFSHTMR
 204         .word   RFSHTMR_NORMAL
 205         .word   GBLCNFG
 206         .word   GC_CMD_MODE
 207         .word   DO_MEM_READ
 208         .word   (SDRAM_BASE | SDRAM_DEVICE_MODE)
 209         .word   GBLCNFG
 210         .word   GC_CMD_NORMAL
 211         .word   SDCSCX_BASE
 212         .word   (SDCSCX_AUTOPC | SDCSCX_RAS2CAS_3 | SDCSCX_CASLAT_3 | SDCSCX_SROMLL | SDCSCX_4BNK | SDCSCX_EBW_32)