board/lwmon5/sdram.c

   1 /*
   2  * (C) Copyright 2006
   3  * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
   4  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   5  * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
   6  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   7  * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
   8  *
   9  * (C) Copyright 2007-2008
  10  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 /* define DEBUG for debugging output (obviously ;-)) */
  29 #if 0
  30 #define DEBUG
  31 #endif
  32
  33 #include <common.h>
  34 #include <asm/processor.h>
  35 #include <asm/mmu.h>
  36 #include <asm/io.h>
  37 #include <ppc440.h>
  38 #include <watchdog.h>
  39
  40 /*
  41  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
  42  * region. Right now the cache should still be disabled in U-Boot because of the
  43  * EMAC driver, that need it's buffer descriptor to be located in non cached
  44  * memory.
  45  *
  46  * If at some time this restriction doesn't apply anymore, just define
  47  * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
  48  * everything correctly.
  49  */
  50 #ifdef CFG_ENABLE_SDRAM_CACHE
  51 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
  52 #else
  53 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
  54 #endif
  55
  56 /*-----------------------------------------------------------------------------+
  57  * Prototypes
  58  *-----------------------------------------------------------------------------*/
  59 extern int denali_wait_for_dlllock(void);
  60 extern void denali_core_search_data_eye(void);
  61 extern void dcbz_area(u32 start_address, u32 num_bytes);
  62 extern void dflush(void);
  63
  64 static u32 is_ecc_enabled(void)
  65 {
  66         u32 val;
  67
  68         mfsdram(DDR0_22, val);
  69         val &= DDR0_22_CTRL_RAW_MASK;
  70         if (val)
  71                 return 1;
  72         else
  73                 return 0;
  74 }
  75
  76 void board_add_ram_info(int use_default)
  77 {
  78         PPC4xx_SYS_INFO board_cfg;
  79         u32 val;
  80
  81         if (is_ecc_enabled())
  82                 puts(" (ECC");
  83         else
  84                 puts(" (ECC not");
  85
  86         get_sys_info(&board_cfg);
  87         printf(" enabled, %d MHz", (board_cfg.freqPLB * 2) / 1000000);
  88
  89         mfsdram(DDR0_03, val);
  90         val = DDR0_03_CASLAT_DECODE(val);
  91         printf(", CL%d)", val);
  92 }
  93
  94 #ifdef CONFIG_DDR_ECC
  95 static void wait_ddr_idle(void)
  96 {
  97         /*
  98          * Controller idle status cannot be determined for Denali
  99          * DDR2 code. Just return here.
 100          */
 101 }
 102
 103 static void program_ecc(u32 start_address,
 104                         u32 num_bytes,
 105                         u32 tlb_word2_i_value)
 106 {
 107         u32 val;
 108         u32 current_addr = start_address;
 109         int bytes_remaining;
 110
 111         sync();
 112         wait_ddr_idle();
 113
 114         /*
 115          * Because of 440EPx errata CHIP 11, we don't touch the last 256
 116          * bytes of SDRAM.
 117          */
 118         bytes_remaining = num_bytes - CFG_MEM_TOP_HIDE;
 119
 120         /*
 121          * We have to write the ECC bytes by zeroing and flushing in smaller
 122          * steps, since the whole 256MByte takes too long for the external
 123          * watchdog.
 124          */
 125         while (bytes_remaining > 0) {
 126                 dcbz_area(current_addr, min((64 << 20), bytes_remaining));
 127                 current_addr += 64 << 20;
 128                 bytes_remaining -= 64 << 20;
 129                 WATCHDOG_RESET();
 130         }
 131         dflush();
 132
 133         sync();
 134         wait_ddr_idle();
 135
 136         /* Clear error status */
 137         mfsdram(DDR0_00, val);
 138         mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
 139
 140         /* Set 'int_mask' parameter to functionnal value */
 141         mfsdram(DDR0_01, val);
 142         mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
 143
 144         sync();
 145         wait_ddr_idle();
 146 }
 147 #endif
 148
 149 /*************************************************************************
 150  *
 151  * initdram -- 440EPx's DDR controller is a DENALI Core
 152  *
 153  ************************************************************************/
 154 long int initdram (int board_type)
 155 {
 156 #if 0 /* test-only: will remove this define later, when ECC problems are solved! */
 157         /* CL=3 */
 158         mtsdram(DDR0_02, 0x00000000);
 159
 160         mtsdram(DDR0_00, 0x0000190A);
 161         mtsdram(DDR0_01, 0x01000000);
 162         mtsdram(DDR0_03, 0x02030603); /* A suitable burst length was taken. CAS is right for our board */
 163
 164         mtsdram(DDR0_04, 0x0A030300);
 165         mtsdram(DDR0_05, 0x02020308);
 166         mtsdram(DDR0_06, 0x0103C812);
 167         mtsdram(DDR0_07, 0x00090100);
 168         mtsdram(DDR0_08, 0x02c80001);
 169         mtsdram(DDR0_09, 0x00011D5F);
 170         mtsdram(DDR0_10, 0x00000300);
 171         mtsdram(DDR0_11, 0x000CC800);
 172         mtsdram(DDR0_12, 0x00000003);
 173         mtsdram(DDR0_14, 0x00000000);
 174         mtsdram(DDR0_17, 0x1e000000);
 175         mtsdram(DDR0_18, 0x1e1e1e1e);
 176         mtsdram(DDR0_19, 0x1e1e1e1e);
 177         mtsdram(DDR0_20, 0x0B0B0B0B);
 178         mtsdram(DDR0_21, 0x0B0B0B0B);
 179 #ifdef CONFIG_DDR_ECC
 180         mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC       */
 181 #else
 182         mtsdram(DDR0_22, 0x00267F0B);
 183 #endif
 184
 185         mtsdram(DDR0_23, 0x01000000);
 186         mtsdram(DDR0_24, 0x01010001);
 187
 188         mtsdram(DDR0_26, 0x2D93028A);
 189         mtsdram(DDR0_27, 0x0784682B);
 190
 191         mtsdram(DDR0_28, 0x00000080);
 192         mtsdram(DDR0_31, 0x00000000);
 193         mtsdram(DDR0_42, 0x01000006);
 194
 195         mtsdram(DDR0_43, 0x030A0200);
 196         mtsdram(DDR0_44, 0x00000003);
 197         mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
 198 #else
 199         /* CL=4 */
 200         mtsdram(DDR0_02, 0x00000000);
 201
 202         mtsdram(DDR0_00, 0x0000190A);
 203         mtsdram(DDR0_01, 0x01000000);
 204         mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
 205
 206         mtsdram(DDR0_04, 0x0B030300);
 207         mtsdram(DDR0_05, 0x02020308);
 208         mtsdram(DDR0_06, 0x0003C812);
 209         mtsdram(DDR0_07, 0x00090100);
 210         mtsdram(DDR0_08, 0x03c80001);
 211         mtsdram(DDR0_09, 0x00011D5F);
 212         mtsdram(DDR0_10, 0x00000300);
 213         mtsdram(DDR0_11, 0x000CC800);
 214         mtsdram(DDR0_12, 0x00000003);
 215         mtsdram(DDR0_14, 0x00000000);
 216         mtsdram(DDR0_17, 0x1e000000);
 217         mtsdram(DDR0_18, 0x1e1e1e1e);
 218         mtsdram(DDR0_19, 0x1e1e1e1e);
 219         mtsdram(DDR0_20, 0x0B0B0B0B);
 220         mtsdram(DDR0_21, 0x0B0B0B0B);
 221 #ifdef CONFIG_DDR_ECC
 222         mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC       */
 223 #else
 224         mtsdram(DDR0_22, 0x00267F0B);
 225 #endif
 226
 227         mtsdram(DDR0_23, 0x01000000);
 228         mtsdram(DDR0_24, 0x01010001);
 229
 230         mtsdram(DDR0_26, 0x2D93028A);
 231         mtsdram(DDR0_27, 0x0784682B);
 232
 233         mtsdram(DDR0_28, 0x00000080);
 234         mtsdram(DDR0_31, 0x00000000);
 235         mtsdram(DDR0_42, 0x01000008);
 236
 237         mtsdram(DDR0_43, 0x050A0200);
 238         mtsdram(DDR0_44, 0x00000005);
 239         mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
 240 #endif
 241
 242         denali_wait_for_dlllock();
 243
 244 #if defined(CONFIG_DDR_DATA_EYE)
 245         /* -----------------------------------------------------------+
 246          * Perform data eye search if requested.
 247          * ----------------------------------------------------------*/
 248         program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
 249                     TLB_WORD2_I_ENABLE);
 250         denali_core_search_data_eye();
 251         remove_tlb(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
 252 #endif
 253
 254         /*
 255          * Program tlb entries for this size (dynamic)
 256          */
 257         program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
 258                     MY_TLB_WORD2_I_ENABLE);
 259
 260         /*
 261          * Setup 2nd TLB with same physical address but different virtual address
 262          * with cache enabled. This is done for fast ECC generation.
 263          */
 264         program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
 265
 266 #ifdef CONFIG_DDR_ECC
 267         /*
 268          * If ECC is enabled, initialize the parity bits.
 269          */
 270         program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
 271 #endif
 272
 273         /*
 274          * Clear possible errors resulting from data-eye-search.
 275          * If not done, then we could get an interrupt later on when
 276          * exceptions are enabled.
 277          */
 278         set_mcsr(get_mcsr());
 279
 280         return (CFG_MBYTES_SDRAM << 20);
 281 }