board/lwmon5/sdram.c

   1 /*
   2  * (C) Copyright 2006
   3  * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
   4  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   5  * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
   6  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   7  * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
   8  *
   9  * (C) Copyright 2007
  10  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 /* define DEBUG for debugging output (obviously ;-)) */
  29 #if 0
  30 #define DEBUG
  31 #endif
  32
  33 #include <common.h>
  34 #include <asm/processor.h>
  35 #include <asm/mmu.h>
  36 #include <asm/io.h>
  37 #include <ppc440.h>
  38
  39 /*
  40  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
  41  * region. Right now the cache should still be disabled in U-Boot because of the
  42  * EMAC driver, that need it's buffer descriptor to be located in non cached
  43  * memory.
  44  *
  45  * If at some time this restriction doesn't apply anymore, just define
  46  * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
  47  * everything correctly.
  48  */
  49 #ifdef CFG_ENABLE_SDRAM_CACHE
  50 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
  51 #else
  52 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
  53 #endif
  54
  55 /*-----------------------------------------------------------------------------+
  56  * Prototypes
  57  *-----------------------------------------------------------------------------*/
  58 extern int denali_wait_for_dlllock(void);
  59 extern void denali_core_search_data_eye(void);
  60 extern void dcbz_area(u32 start_address, u32 num_bytes);
  61 extern void dflush(void);
  62
  63 static u32 is_ecc_enabled(void)
  64 {
  65         u32 val;
  66
  67         mfsdram(DDR0_22, val);
  68         val &= DDR0_22_CTRL_RAW_MASK;
  69         if (val)
  70                 return 1;
  71         else
  72                 return 0;
  73 }
  74
  75 void board_add_ram_info(int use_default)
  76 {
  77         PPC4xx_SYS_INFO board_cfg;
  78         u32 val;
  79
  80         if (is_ecc_enabled())
  81                 puts(" (ECC");
  82         else
  83                 puts(" (ECC not");
  84
  85         get_sys_info(&board_cfg);
  86         printf(" enabled, %d MHz", (board_cfg.freqPLB * 2) / 1000000);
  87
  88         mfsdram(DDR0_03, val);
  89         val = DDR0_03_CASLAT_DECODE(val);
  90         printf(", CL%d)", val);
  91 }
  92
  93 #ifdef CONFIG_DDR_ECC
  94 static void wait_ddr_idle(void)
  95 {
  96         /*
  97          * Controller idle status cannot be determined for Denali
  98          * DDR2 code. Just return here.
  99          */
 100 }
 101
 102 static void blank_string(int size)
 103 {
 104         int i;
 105
 106         for (i=0; i<size; i++)
 107                 putc('\b');
 108         for (i=0; i<size; i++)
 109                 putc(' ');
 110         for (i=0; i<size; i++)
 111                 putc('\b');
 112 }
 113
 114 static void program_ecc(u32 start_address,
 115                         u32 num_bytes,
 116                         u32 tlb_word2_i_value)
 117 {
 118         u32 current_address;
 119         u32 end_address;
 120         u32 address_increment;
 121         u32 val;
 122         char str[] = "ECC generation -";
 123         char slash[] = "\\|/-\\|/-";
 124         int loop = 0;
 125         int loopi = 0;
 126
 127         current_address = start_address;
 128
 129         sync();
 130         eieio();
 131         wait_ddr_idle();
 132
 133         if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
 134                 /* ECC bit set method for non-cached memory */
 135                 address_increment = 4;
 136                 end_address = current_address + num_bytes;
 137
 138                 puts(str);
 139
 140                 while (current_address < end_address) {
 141                         *((u32 *)current_address) = 0x00000000;
 142                         current_address += address_increment;
 143
 144                         if ((loop++ % (2 << 20)) == 0) {
 145                                 putc('\b');
 146                                 putc(slash[loopi++ % 8]);
 147                         }
 148                 }
 149
 150                 blank_string(strlen(str));
 151         } else {
 152                 /* ECC bit set method for cached memory */
 153 #if 0 /* test-only: will remove this define later, when ECC problems are solved! */
 154                 /*
 155                  * Some boards (like lwmon5) need to preserve the memory
 156                  * content upon ECC generation (for the log-buffer).
 157                  * Therefore we don't fill the memory with a pattern or
 158                  * just zero it, but write the same values back that are
 159                  * already in the memory cells.
 160                  */
 161                 address_increment = CFG_CACHELINE_SIZE;
 162                 end_address = current_address + num_bytes;
 163
 164                 current_address = start_address;
 165                 while (current_address < end_address) {
 166                         /*
 167                          * TODO: Th following sequence doesn't work correctly.
 168                          * Just invalidating and flushing the cache doesn't
 169                          * seem to trigger the re-write of the memory.
 170                          */
 171                         ppcDcbi(current_address);
 172                         ppcDcbf(current_address);
 173                         current_address += CFG_CACHELINE_SIZE;
 174                 }
 175 #else
 176                 dcbz_area(start_address, num_bytes);
 177                 dflush();
 178 #endif
 179         }
 180
 181         sync();
 182         eieio();
 183         wait_ddr_idle();
 184
 185         /* Clear error status */
 186         mfsdram(DDR0_00, val);
 187         mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
 188
 189         /* Set 'int_mask' parameter to functionnal value */
 190         mfsdram(DDR0_01, val);
 191         mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
 192
 193         sync();
 194         eieio();
 195         wait_ddr_idle();
 196 }
 197 #endif
 198
 199 /*************************************************************************
 200  *
 201  * initdram -- 440EPx's DDR controller is a DENALI Core
 202  *
 203  ************************************************************************/
 204 long int initdram (int board_type)
 205 {
 206 #if 0 /* test-only: will remove this define later, when ECC problems are solved! */
 207         /* CL=3 */
 208         mtsdram(DDR0_02, 0x00000000);
 209
 210         mtsdram(DDR0_00, 0x0000190A);
 211         mtsdram(DDR0_01, 0x01000000);
 212         mtsdram(DDR0_03, 0x02030603); /* A suitable burst length was taken. CAS is right for our board */
 213
 214         mtsdram(DDR0_04, 0x0A030300);
 215         mtsdram(DDR0_05, 0x02020308);
 216         mtsdram(DDR0_06, 0x0103C812);
 217         mtsdram(DDR0_07, 0x00090100);
 218         mtsdram(DDR0_08, 0x02c80001);
 219         mtsdram(DDR0_09, 0x00011D5F);
 220         mtsdram(DDR0_10, 0x00000300);
 221         mtsdram(DDR0_11, 0x000CC800);
 222         mtsdram(DDR0_12, 0x00000003);
 223         mtsdram(DDR0_14, 0x00000000);
 224         mtsdram(DDR0_17, 0x1e000000);
 225         mtsdram(DDR0_18, 0x1e1e1e1e);
 226         mtsdram(DDR0_19, 0x1e1e1e1e);
 227         mtsdram(DDR0_20, 0x0B0B0B0B);
 228         mtsdram(DDR0_21, 0x0B0B0B0B);
 229 #ifdef CONFIG_DDR_ECC
 230         mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC       */
 231 #else
 232         mtsdram(DDR0_22, 0x00267F0B);
 233 #endif
 234
 235         mtsdram(DDR0_23, 0x01000000);
 236         mtsdram(DDR0_24, 0x01010001);
 237
 238         mtsdram(DDR0_26, 0x2D93028A);
 239         mtsdram(DDR0_27, 0x0784682B);
 240
 241         mtsdram(DDR0_28, 0x00000080);
 242         mtsdram(DDR0_31, 0x00000000);
 243         mtsdram(DDR0_42, 0x01000006);
 244
 245         mtsdram(DDR0_43, 0x030A0200);
 246         mtsdram(DDR0_44, 0x00000003);
 247         mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
 248 #else
 249         /* CL=4 */
 250         mtsdram(DDR0_02, 0x00000000);
 251
 252         mtsdram(DDR0_00, 0x0000190A);
 253         mtsdram(DDR0_01, 0x01000000);
 254         mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
 255
 256         mtsdram(DDR0_04, 0x0B030300);
 257         mtsdram(DDR0_05, 0x02020308);
 258         mtsdram(DDR0_06, 0x0003C812);
 259         mtsdram(DDR0_07, 0x00090100);
 260         mtsdram(DDR0_08, 0x03c80001);
 261         mtsdram(DDR0_09, 0x00011D5F);
 262         mtsdram(DDR0_10, 0x00000300);
 263         mtsdram(DDR0_11, 0x000CC800);
 264         mtsdram(DDR0_12, 0x00000003);
 265         mtsdram(DDR0_14, 0x00000000);
 266         mtsdram(DDR0_17, 0x1e000000);
 267         mtsdram(DDR0_18, 0x1e1e1e1e);
 268         mtsdram(DDR0_19, 0x1e1e1e1e);
 269         mtsdram(DDR0_20, 0x0B0B0B0B);
 270         mtsdram(DDR0_21, 0x0B0B0B0B);
 271 #ifdef CONFIG_DDR_ECC
 272         mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC       */
 273 #else
 274         mtsdram(DDR0_22, 0x00267F0B);
 275 #endif
 276
 277         mtsdram(DDR0_23, 0x01000000);
 278         mtsdram(DDR0_24, 0x01010001);
 279
 280         mtsdram(DDR0_26, 0x2D93028A);
 281         mtsdram(DDR0_27, 0x0784682B);
 282
 283         mtsdram(DDR0_28, 0x00000080);
 284         mtsdram(DDR0_31, 0x00000000);
 285         mtsdram(DDR0_42, 0x01000008);
 286
 287         mtsdram(DDR0_43, 0x050A0200);
 288         mtsdram(DDR0_44, 0x00000005);
 289         mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
 290 #endif
 291
 292         denali_wait_for_dlllock();
 293
 294 #if defined(CONFIG_DDR_DATA_EYE)
 295         /* -----------------------------------------------------------+
 296          * Perform data eye search if requested.
 297          * ----------------------------------------------------------*/
 298         program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
 299                     TLB_WORD2_I_ENABLE);
 300         denali_core_search_data_eye();
 301         remove_tlb(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
 302 #endif
 303
 304         /*
 305          * Program tlb entries for this size (dynamic)
 306          */
 307         program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
 308                     MY_TLB_WORD2_I_ENABLE);
 309
 310         /*
 311          * Setup 2nd TLB with same physical address but different virtual address
 312          * with cache enabled. This is done for fast ECC generation.
 313          */
 314         program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
 315
 316 #ifdef CONFIG_DDR_ECC
 317         /*
 318          * If ECC is enabled, initialize the parity bits.
 319          */
 320         program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
 321 #endif
 322
 323         /*
 324          * Clear possible errors resulting from data-eye-search.
 325          * If not done, then we could get an interrupt later on when
 326          * exceptions are enabled.
 327          */
 328         set_mcsr(get_mcsr());
 329
 330         return (CFG_MBYTES_SDRAM << 20);
 331 }