board/matrix_vision/mvbc_p/mvbc_p.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * (C) Copyright 2005-2007
   9  * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <common.h>
  15 #include <mpc5xxx.h>
  16 #include <malloc.h>
  17 #include <pci.h>
  18 #include <i2c.h>
  19 #include <fpga.h>
  20 #include <environment.h>
  21 #include <fdt_support.h>
  22 #include <netdev.h>
  23 #include <asm/io.h>
  24 #include "fpga.h"
  25 #include "mvbc_p.h"
  26 #include "../common/mv_common.h"
  27
  28 #define SDRAM_MODE      0x00CD0000
  29 #define SDRAM_CONTROL   0x504F0000
  30 #define SDRAM_CONFIG1   0xD2322800
  31 #define SDRAM_CONFIG2   0x8AD70000
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 static void sdram_start (int hi_addr)
  36 {
  37         long hi_bit = hi_addr ? 0x01000000 : 0;
  38
  39         /* unlock mode register */
  40         out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit);
  41
  42         /* precharge all banks */
  43         out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
  44
  45         /* precharge all banks */
  46         out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
  47
  48         /* auto refresh */
  49         out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit);
  50
  51         /* set mode register */
  52         out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
  53
  54         /* normal operation */
  55         out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
  56 }
  57
  58 phys_addr_t initdram (int board_type)
  59 {
  60         ulong dramsize = 0;
  61         ulong test1,
  62               test2;
  63
  64         /* setup SDRAM chip selects */
  65         out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
  66
  67         /* setup config registers */
  68         out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
  69         out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
  70
  71         /* find RAM size using SDRAM CS0 only */
  72         sdram_start(0);
  73         test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
  74         sdram_start(1);
  75         test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
  76         if (test1 > test2) {
  77                 sdram_start(0);
  78                 dramsize = test1;
  79         } else
  80                 dramsize = test2;
  81
  82         if (dramsize < (1 << 20))
  83                 dramsize = 0;
  84
  85         if (dramsize > 0)
  86                 out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 +
  87                         __builtin_ffs(dramsize >> 20) - 1);
  88         else
  89                 out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0);
  90
  91         return dramsize;
  92 }
  93
  94 void mvbc_init_gpio(void)
  95 {
  96         struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
  97
  98         printf("Ports : 0x%08x\n", gpio->port_config);
  99         printf("PORCFG: 0x%08lx\n", *(vu_long*)MPC5XXX_CDM_PORCFG);
 100
 101         out_be32(&gpio->simple_ddr, SIMPLE_DDR);
 102         out_be32(&gpio->simple_dvo, SIMPLE_DVO);
 103         out_be32(&gpio->simple_ode, SIMPLE_ODE);
 104         out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
 105
 106         out_8(&gpio->sint_ode, SINT_ODE);
 107         out_8(&gpio->sint_ddr, SINT_DDR);
 108         out_8(&gpio->sint_dvo, SINT_DVO);
 109         out_8(&gpio->sint_inten, SINT_INTEN);
 110         out_be16(&gpio->sint_itype, SINT_ITYPE);
 111         out_8(&gpio->sint_gpioe, SINT_GPIOEN);
 112
 113         out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE);
 114         out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR);
 115         out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO);
 116         out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN);
 117
 118         printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe);
 119         printf("sint_gpioe  : 0x%08x\n", gpio->sint_gpioe);
 120 }
 121
 122 int misc_init_r(void)
 123 {
 124         char *s = getenv("reset_env");
 125
 126         if (!s) {
 127                 if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
 128                         return 0;
 129                 udelay(50000);
 130                 if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
 131                         return 0;
 132                 udelay(50000);
 133                 if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
 134                         return 0;
 135         }
 136         printf(" === FACTORY RESET ===\n");
 137         mv_reset_environment();
 138         saveenv();
 139
 140         return -1;
 141 }
 142
 143 int checkboard(void)
 144 {
 145         mvbc_init_gpio();
 146         printf("Board: Matrix Vision mvBlueCOUGAR-P\n");
 147
 148         return 0;
 149 }
 150
 151 void flash_preinit(void)
 152 {
 153         /*
 154          * Now, when we are in RAM, enable flash write
 155          * access for detection process.
 156          * Note that CS_BOOT cannot be cleared when
 157          * executing in flash.
 158          */
 159         clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1);
 160 }
 161
 162 void flash_afterinit(ulong size)
 163 {
 164         out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_BOOTCS_START |
 165                 size));
 166         out_be32((u32*)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_BOOTCS_START |
 167                 size));
 168         out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
 169                 size));
 170         out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
 171                 size));
 172 }
 173
 174 void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 175 {
 176         unsigned char line = 0xff;
 177         char *s = getenv("pci_latency");
 178         u32 base;
 179         u8 val = 0;
 180
 181         if (s)
 182                 val = simple_strtoul(s, NULL, 16);
 183
 184         if (PCI_BUS(dev) == 0) {
 185                 switch (PCI_DEV (dev)) {
 186                 case 0xa: /* FPGA */
 187                         line = 3;
 188                         pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base);
 189                         printf("found FPGA - enable arbitration\n");
 190                         writel(0x03, (u32*)(base + 0x80c0));
 191                         writel(0xf0, (u32*)(base + 0x8080));
 192                         if (val)
 193                                 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
 194                         break;
 195                 case 0xb: /* LAN */
 196                         line = 2;
 197                         if (val)
 198                                 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
 199                         break;
 200                 case 0x1a:
 201                         break;
 202                 default:
 203                         printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev));
 204                         break;
 205                 }
 206                 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
 207         }
 208 }
 209
 210 struct pci_controller hose = {
 211         fixup_irq:pci_mvbc_fixup_irq
 212 };
 213
 214 extern void pci_mpc5xxx_init(struct pci_controller *);
 215
 216 void pci_init_board(void)
 217 {
 218         mvbc_p_init_fpga();
 219         mv_load_fpga();
 220         pci_mpc5xxx_init(&hose);
 221 }
 222
 223 void show_boot_progress(int val)
 224 {
 225         struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
 226
 227         switch(val) {
 228         case BOOTSTAGE_ID_START: /* FPGA ok */
 229                 setbits_be32(&gpio->simple_dvo, LED_G0);
 230                 break;
 231         case BOOTSTAGE_ID_NET_ETH_INIT:
 232                 setbits_be32(&gpio->simple_dvo, LED_G1);
 233                 break;
 234         case BOOTSTAGE_ID_COPY_RAMDISK:
 235                 setbits_be32(&gpio->simple_dvo, LED_Y);
 236                 break;
 237         case BOOTSTAGE_ID_RUN_OS:
 238                 setbits_be32(&gpio->simple_dvo, LED_R);
 239                 break;
 240         default:
 241                 break;
 242         }
 243
 244 }
 245
 246 void ft_board_setup(void *blob, bd_t *bd)
 247 {
 248         ft_cpu_setup(blob, bd);
 249 }
 250
 251 int board_eth_init(bd_t *bis)
 252 {
 253         cpu_eth_init(bis); /* Built in FEC comes first */
 254         return pci_eth_init(bis);
 255 }