board/matrix_vision/mvblm7/pci.c

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   3  *
   4  * (C) Copyright 2008
   5  * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #if defined(CONFIG_OF_LIBFDT)
  28 #include <libfdt.h>
  29 #endif
  30 #include <pci.h>
  31 #include <mpc83xx.h>
  32 #include <fpga.h>
  33 #include "mvblm7.h"
  34 #include "fpga.h"
  35 #include "../common/mv_common.h"
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 static struct pci_region pci_regions[] = {
  40         {
  41                 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
  42                 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
  43                 size: CONFIG_SYS_PCI1_MEM_SIZE,
  44                 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  45         },
  46         {
  47                 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
  48                 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
  49                 size: CONFIG_SYS_PCI1_MMIO_SIZE,
  50                 flags: PCI_REGION_MEM
  51         },
  52         {
  53                 bus_start: CONFIG_SYS_PCI1_IO_BASE,
  54                 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
  55                 size: CONFIG_SYS_PCI1_IO_SIZE,
  56                 flags: PCI_REGION_IO
  57         }
  58 };
  59
  60 void pci_init_board(void)
  61 {
  62         int i;
  63         int warmboot;
  64         volatile immap_t *immr;
  65         volatile pcictrl83xx_t *pci_ctrl;
  66         volatile gpio83xx_t *gpio;
  67         volatile clk83xx_t *clk;
  68         volatile law83xx_t *pci_law;
  69         struct pci_region *reg[] = { pci_regions };
  70
  71         immr = (immap_t *) CONFIG_SYS_IMMR;
  72         clk = (clk83xx_t *) &immr->clk;
  73         pci_ctrl = immr->pci_ctrl;
  74         pci_law = immr->sysconf.pcilaw;
  75         gpio  = (volatile gpio83xx_t *)&immr->gpio[0];
  76
  77         gpio->dat = MV_GPIO_DAT;
  78         gpio->odr = MV_GPIO_ODE;
  79         gpio->dir = MV_GPIO_OUT;
  80
  81         printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
  82                 immr->sysconf.sicrl);
  83
  84         mvblm7_init_fpga();
  85         mv_load_fpga();
  86
  87         gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
  88
  89         /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
  90         clk->occr = 0xc0000000;
  91
  92         pci_ctrl[0].gcr = 0;
  93         udelay(2000);
  94         pci_ctrl[0].gcr = 1;
  95
  96         for (i = 0; i < 1000; ++i)
  97                 udelay(1000);
  98
  99         pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 100         pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB;
 101
 102         pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 103         pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
 104
 105         warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
 106
 107         mpc83xx_pci_init(1, reg, warmboot);
 108 }