board/matrix_vision/mvsmr/mvsmr.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * (C) Copyright 2005-2010
   9  * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <common.h>
  15 #include <mpc5xxx.h>
  16 #include <malloc.h>
  17 #include <pci.h>
  18 #include <i2c.h>
  19 #include <fpga.h>
  20 #include <environment.h>
  21 #include <netdev.h>
  22 #include <asm/io.h>
  23 #include "fpga.h"
  24 #include "mvsmr.h"
  25 #include "../common/mv_common.h"
  26
  27 #define SDRAM_DDR       1
  28 #define SDRAM_MODE      0x018D0000
  29 #define SDRAM_EMODE     0x40090000
  30 #define SDRAM_CONTROL   0x715f0f00
  31 #define SDRAM_CONFIG1   0xd3722930
  32 #define SDRAM_CONFIG2   0x46770000
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 static void sdram_start(int hi_addr)
  37 {
  38         long hi_bit = hi_addr ? 0x01000000 : 0;
  39
  40         /* unlock mode register */
  41         out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 |
  42                 hi_bit);
  43
  44         /* precharge all banks */
  45         out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
  46                 hi_bit);
  47
  48         /* set mode register: extended mode */
  49         out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
  50
  51         /* set mode register: reset DLL */
  52         out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
  53
  54         /* precharge all banks */
  55         out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
  56                 hi_bit);
  57
  58         /* auto refresh */
  59         out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 |
  60                 hi_bit);
  61
  62         /* set mode register */
  63         out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
  64
  65         /* normal operation */
  66         out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
  67 }
  68
  69 phys_addr_t initdram(int board_type)
  70 {
  71         ulong dramsize = 0;
  72         ulong test1,
  73               test2;
  74
  75         /* setup SDRAM chip selects */
  76         out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
  77
  78         /* setup config registers */
  79         out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
  80         out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
  81
  82         /* find RAM size using SDRAM CS0 only */
  83         sdram_start(0);
  84         test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
  85         sdram_start(1);
  86         test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
  87         if (test1 > test2) {
  88                 sdram_start(0);
  89                 dramsize = test1;
  90         } else
  91                 dramsize = test2;
  92
  93         if (dramsize < (1 << 20))
  94                 dramsize = 0;
  95
  96         if (dramsize > 0)
  97                 out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 +
  98                         __builtin_ffs(dramsize >> 20) - 1);
  99         else
 100                 out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0);
 101
 102         return dramsize;
 103 }
 104
 105 void mvsmr_init_gpio(void)
 106 {
 107         struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 108         struct mpc5xxx_wu_gpio *wu_gpio =
 109                 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 110         struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
 111
 112         printf("Ports : 0x%08x\n", gpio->port_config);
 113         printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG));
 114
 115         out_be32(&gpio->simple_ddr, SIMPLE_DDR);
 116         out_be32(&gpio->simple_dvo, SIMPLE_DVO);
 117         out_be32(&gpio->simple_ode, SIMPLE_ODE);
 118         out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
 119
 120         out_8(&gpio->sint_ode, SINT_ODE);
 121         out_8(&gpio->sint_ddr, SINT_DDR);
 122         out_8(&gpio->sint_dvo, SINT_DVO);
 123         out_8(&gpio->sint_inten, SINT_INTEN);
 124         out_be16(&gpio->sint_itype, SINT_ITYPE);
 125         out_8(&gpio->sint_gpioe, SINT_GPIOEN);
 126
 127         out_8(&wu_gpio->ode, WKUP_ODE);
 128         out_8(&wu_gpio->ddr, WKUP_DIR);
 129         out_8(&wu_gpio->dvo, WKUP_DO);
 130         out_8(&wu_gpio->enable, WKUP_EN);
 131
 132         out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */
 133         out_be32(&timers->gpt1.emsr, 0x00000234);
 134         out_be32(&timers->gpt2.emsr, 0x00000234);
 135         out_be32(&timers->gpt3.emsr, 0x00000234);
 136         out_be32(&timers->gpt4.emsr, 0x00000234);
 137         out_be32(&timers->gpt5.emsr, 0x00000234);
 138         out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */
 139         out_be32(&timers->gpt7.emsr, 0x00000024);
 140 }
 141
 142 int misc_init_r(void)
 143 {
 144         char *s = getenv("reset_env");
 145
 146         if (s) {
 147                 printf(" === FACTORY RESET ===\n");
 148                 mv_reset_environment();
 149                 saveenv();
 150         }
 151
 152         return -1;
 153 }
 154
 155 void mvsmr_get_dbg_present(void)
 156 {
 157         struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 158         struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
 159
 160         if (in_be32(&gpio->simple_ival) & COP_PRESENT) {
 161                 setenv("dbg_present", "no\0");
 162                 setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0");
 163         } else {
 164                 setenv("dbg_present", "yes\0");
 165                 setenv("bootstopkey", "s\0");
 166                 setbits_8(&psc->command, PSC_RX_ENABLE);
 167         }
 168 }
 169
 170 void mvsmr_get_service_mode(void)
 171 {
 172         struct mpc5xxx_wu_gpio *wu_gpio =
 173                 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 174
 175         if (in_8(&wu_gpio->ival) & SERVICE_MODE)
 176                 setenv("servicemode", "no\0");
 177         else
 178                 setenv("servicemode", "yes\0");
 179 }
 180
 181 int mvsmr_get_mac(void)
 182 {
 183         unsigned char mac[6];
 184         struct mpc5xxx_wu_gpio *wu_gpio =
 185                 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 186
 187         if (in_8(&wu_gpio->ival) & LAN_PRSNT) {
 188                 setenv("lan_present", "no\0");
 189                 return -1;
 190         } else
 191                 setenv("lan_present", "yes\0");
 192
 193         i2c_read(0x50, 0, 1, mac, 6);
 194
 195         eth_setenv_enetaddr("ethaddr", mac);
 196
 197         return 0;
 198 }
 199
 200 int checkboard(void)
 201 {
 202         mvsmr_init_gpio();
 203         printf("Board: Matrix Vision mvSMR\n");
 204
 205         return 0;
 206 }
 207
 208 void flash_preinit(void)
 209 {
 210         /*
 211          * Now, when we are in RAM, enable flash write
 212          * access for detection process.
 213          * Note that CS_BOOT cannot be cleared when
 214          * executing in flash.
 215          */
 216         clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1);
 217 }
 218
 219 void flash_afterinit(ulong size)
 220 {
 221         out_be32((u32 *)MPC5XXX_BOOTCS_START,
 222                 START_REG(CONFIG_SYS_BOOTCS_START | size));
 223         out_be32((u32 *)MPC5XXX_CS0_START,
 224                 START_REG(CONFIG_SYS_BOOTCS_START | size));
 225         out_be32((u32 *)MPC5XXX_BOOTCS_STOP,
 226                 STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
 227         out_be32((u32 *)MPC5XXX_CS0_STOP,
 228                 STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
 229 }
 230
 231 struct pci_controller hose;
 232
 233 void pci_init_board(void)
 234 {
 235         mvsmr_get_dbg_present();
 236         mvsmr_get_service_mode();
 237         mvsmr_init_fpga();
 238         mv_load_fpga();
 239         pci_mpc5xxx_init(&hose);
 240 }
 241
 242 int board_eth_init(bd_t *bis)
 243 {
 244         if (!mvsmr_get_mac())
 245                 return cpu_eth_init(bis);
 246
 247         return pci_eth_init(bis);
 248 }