board/mbx8xx/csr.h

   1 #ifndef __csr_h
   2 #define __csr_h
   3
   4 /*
   5  * (C) Copyright 2000
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * Control and Status Register definitions for the MBX
  10  *
  11  *--------------------------------------------------------------------
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 /* bits for control register #1 / status register #1 */
  16 #define CSR1_ETEN       0x80    /* Ethernet Transceiver Enabled             */
  17 #define CSR1_ELEN       0x40    /* Ethernet XCVR in Internal Loopback       */
  18 #define CSR1_EAEN       0x20    /* Auto selection TP/AUI Enabled            */
  19 #define CSR1_TPEN       0x10    /* TP manually selected                     */
  20 #define CSR1_FDDIS      0x08    /* Full Duplex Mode disabled                */
  21 #define CSR1_FCTEN      0x04    /* Collision Testing of XCVR disabled       */
  22 #define CSR1_COM1EN     0x02    /* COM1 signals routed to RS232 Transceiver */
  23 #define CSR1_XCVRDIS    0x01    /* Onboard RS232 Transceiver Disabled       */
  24
  25 /* bits for control register #2 */
  26 #define CR2_VDDSEL      0xC0    /* PCMCIA Supply Voltage                    */
  27 #define CR2_VPPSEL      0x30    /* PCMCIA Programming Voltage               */
  28 #define CR2_BRDFAIL     0x08    /* Board fail                               */
  29 #define CR2_SWS1        0x04    /* Software Status #2 LED                   */
  30 #define CR2_SWS2        0x02    /* Software Status #2 LED                   */
  31 #define CR2_QSPANRST    0x01    /* Reset QSPAN                              */
  32
  33 /* bits for status register #2 */
  34 #define SR2_VDDSEL      0xC0    /* PCMCIA Supply Voltage                    */
  35 #define SR2_VPPSEL      0x30    /* PCMCIA Programming Voltage               */
  36 #define SR2_BATGD       0x08    /* Low Voltage indication for onboard bat   */
  37 #define SR2_NVBATGD     0x04    /* Low Voltage indication for NVRAM         */
  38 #define SR2_RDY         0x02    /* Flash programming status bit             */
  39 #define SR2_FT          0x01    /* Reserved for Factory test purposes       */
  40
  41 #define MBX_CSR1 (*((uchar *)CONFIG_SYS_CSR_BASE))
  42 #define MBX_CSR2 (*((uchar *)CONFIG_SYS_CSR_BASE + 1))
  43
  44 #endif /* __csr_h */