board/mcc200/mcc200.c

   1 /*
   2  * (C) Copyright 2003-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <mpc5xxx.h>
  29 #include <pci.h>
  30
  31 #include "mt48lc8m32b2-6-7.h"
  32
  33 extern flash_info_t flash_info[];       /* FLASH chips info */
  34
  35 ulong flash_get_size (ulong base, int banknum);
  36
  37 #ifndef CFG_RAMBOOT
  38 static void sdram_start (int hi_addr)
  39 {
  40         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  41
  42         /* unlock mode register */
  43         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  44         __asm__ volatile ("sync");
  45
  46         /* precharge all banks */
  47         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  48         __asm__ volatile ("sync");
  49
  50 #if SDRAM_DDR
  51         /* set mode register: extended mode */
  52         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  53         __asm__ volatile ("sync");
  54
  55         /* set mode register: reset DLL */
  56         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  57         __asm__ volatile ("sync");
  58 #endif
  59
  60         /* precharge all banks */
  61         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  62         __asm__ volatile ("sync");
  63
  64         /* auto refresh */
  65         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
  66         __asm__ volatile ("sync");
  67
  68         /* set mode register */
  69         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  70         __asm__ volatile ("sync");
  71
  72         /* normal operation */
  73         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  74         __asm__ volatile ("sync");
  75 }
  76 #endif
  77
  78 /*
  79  * ATTENTION: Although partially referenced initdram does NOT make real use
  80  *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
  81  *            is something else than 0x00000000.
  82  */
  83
  84 long int initdram (int board_type)
  85 {
  86         ulong dramsize = 0;
  87         ulong dramsize2 = 0;
  88 #ifndef CFG_RAMBOOT
  89         ulong test1, test2;
  90
  91         /* setup SDRAM chip selects */
  92         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
  93         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
  94         __asm__ volatile ("sync");
  95
  96         /* setup config registers */
  97         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
  98         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
  99         __asm__ volatile ("sync");
 100
 101 #if SDRAM_DDR
 102         /* set tap delay */
 103         *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 104         __asm__ volatile ("sync");
 105 #endif
 106
 107         /* find RAM size using SDRAM CS0 only */
 108         sdram_start(0);
 109         test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 110         sdram_start(1);
 111         test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 112         if (test1 > test2) {
 113                 sdram_start(0);
 114                 dramsize = test1;
 115         } else {
 116                 dramsize = test2;
 117         }
 118
 119         /* memory smaller than 1MB is impossible */
 120         if (dramsize < (1 << 20)) {
 121                 dramsize = 0;
 122         }
 123
 124         /* set SDRAM CS0 size according to the amount of RAM found */
 125         if (dramsize > 0) {
 126                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
 127         } else {
 128                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 129         }
 130
 131         /* let SDRAM CS1 start right after CS0 */
 132         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
 133
 134         /* find RAM size using SDRAM CS1 only */
 135         if (!dramsize)
 136                 sdram_start(0);
 137         test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 138         if (!dramsize) {
 139                 sdram_start(1);
 140                 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 141         }
 142         if (test1 > test2) {
 143                 sdram_start(0);
 144                 dramsize2 = test1;
 145         } else {
 146                 dramsize2 = test2;
 147         }
 148
 149         /* memory smaller than 1MB is impossible */
 150         if (dramsize2 < (1 << 20)) {
 151                 dramsize2 = 0;
 152         }
 153
 154         /* set SDRAM CS1 size according to the amount of RAM found */
 155         if (dramsize2 > 0) {
 156                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 157                         | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 158         } else {
 159                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 160         }
 161
 162 #else /* CFG_RAMBOOT */
 163
 164         /* retrieve size of memory connected to SDRAM CS0 */
 165         dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 166         if (dramsize >= 0x13) {
 167                 dramsize = (1 << (dramsize - 0x13)) << 20;
 168         } else {
 169                 dramsize = 0;
 170         }
 171
 172         /* retrieve size of memory connected to SDRAM CS1 */
 173         dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 174         if (dramsize2 >= 0x13) {
 175                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 176         } else {
 177                 dramsize2 = 0;
 178         }
 179
 180 #endif /* CFG_RAMBOOT */
 181
 182         return dramsize + dramsize2;
 183 }
 184
 185 int checkboard (void)
 186 {
 187         puts ("Board: MCC200\n");
 188         return 0;
 189 }
 190
 191 int misc_init_r (void)
 192 {
 193         DECLARE_GLOBAL_DATA_PTR;
 194
 195         /*
 196          * Adjust flash start and offset to detected values
 197          */
 198         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 199         gd->bd->bi_flashoffset = 0;
 200
 201         /*
 202          * Check if boot FLASH isn't max size
 203          */
 204         if (gd->bd->bi_flashsize < (0 - CFG_FLASH_BASE)) {
 205                 /* adjust mapping */
 206                 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
 207                         START_REG(gd->bd->bi_flashstart);
 208                 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 209                         STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
 210
 211                 /*
 212                  * Re-check to get correct base address
 213                  */
 214                 flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
 215
 216                 /*
 217                  * Re-do flash protection upon new addresses
 218                  */
 219                 flash_protect (FLAG_PROTECT_CLEAR,
 220                                gd->bd->bi_flashstart, 0xffffffff,
 221                                &flash_info[CFG_MAX_FLASH_BANKS - 1]);
 222
 223                 /* Monitor protection ON by default */
 224                 flash_protect (FLAG_PROTECT_SET,
 225                                CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
 226                                &flash_info[CFG_MAX_FLASH_BANKS - 1]);
 227
 228                 /* Environment protection ON by default */
 229                 flash_protect (FLAG_PROTECT_SET,
 230                                CFG_ENV_ADDR,
 231                                CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
 232                                &flash_info[CFG_MAX_FLASH_BANKS - 1]);
 233
 234                 /* Redundant environment protection ON by default */
 235                 flash_protect (FLAG_PROTECT_SET,
 236                                CFG_ENV_ADDR_REDUND,
 237                                CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
 238                                &flash_info[CFG_MAX_FLASH_BANKS - 1]);
 239         }
 240
 241         return (0);
 242 }
 243
 244 #ifdef  CONFIG_PCI
 245 static struct pci_controller hose;
 246
 247 extern void pci_mpc5xxx_init(struct pci_controller *);
 248
 249 void pci_init_board(void)
 250 {
 251         pci_mpc5xxx_init(&hose);
 252 }
 253 #endif
 254
 255 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
 256
 257 void init_ide_reset (void)
 258 {
 259         debug ("init_ide_reset\n");
 260
 261 }
 262
 263 void ide_set_reset (int idereset)
 264 {
 265         debug ("ide_reset(%d)\n", idereset);
 266
 267 }
 268 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
 269
 270 #if (CONFIG_COMMANDS & CFG_CMD_DOC)
 271 extern void doc_probe (ulong physadr);
 272 void doc_init (void)
 273 {
 274         doc_probe (CFG_DOC_BASE);
 275 }
 276 #endif