board/micronas/vct/ebi.h

   1 /*
   2  * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __EBI__
   8 #define __EBI__
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include "vct.h"
  13
  14 #define EXT_DEVICE_CHANNEL_3    (0x30000000)
  15 #define EXT_DEVICE_CHANNEL_2    (0x20000000)
  16 #define EXT_DEVICE_CHANNEL_1    (0x10000000)
  17 #define EXT_CPU_ACCESS_ACTIVE   (0x00000001)
  18 #define EXT_DMA_ACCESS_ACTIVE   (1 << 14)
  19 #define EXT_CPU_IORDY_SL        (0x00000001)
  20
  21 #define EBI_CPU_WRITE           (1 << 31)
  22 #define EBI_CPU_ID_SHIFT        (28)
  23 #define EBI_CPU_ADDR_MASK       ~(~0UL << EBI_CPU_ID_SHIFT)
  24
  25 /* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD1 */
  26 #define ADDR_LATCH_ENABLE       0
  27 #define ADDR_ACTIVATION         4
  28 #define CHIP_SELECT_START       8
  29 #define OUTPUT_ENABLE_START     12
  30 #define WAIT_TIME               28
  31 #define READ_DURATION           20
  32
  33 /* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD2 */
  34 #define OUTPUT_ENABLE_END       0
  35 #define CHIP_SELECT_END         4
  36 #define ADDR_DEACTIVATION       8
  37 #define RECOVER_TIME            12
  38 #define ACK_TIME                20
  39
  40 /* various bits in configuration register EBI_DEV[01]_CONFIG1 */
  41 #define EBI_EXTERNAL_DATA_8     (1 <<  8)
  42 #define EBI_EXT_ADDR_SHIFT      (1 << 22)
  43 #define EBI_EXTERNAL_DATA_16    EBI_EXT_ADDR_SHIFT
  44 #define EBI_CHIP_SELECT_1       0x2
  45 #define EBI_CHIP_SELECT_2       0x4
  46 #define EBI_BUSY_EN_RD          (1 << 12)
  47 #define DIR_ACCESS_WRITE        (1 << 20)
  48 #define DIR_ACCESS_MASK         (1 << 20)
  49
  50 /* various bits in configuration register EBI_DEV[01]_CONFIG2 */
  51 #define ADDRESS_INCREMENT_ON    0x0
  52 #define ADDRESS_INCREMENT_OFF   0x100
  53 #define QUEUE_LENGTH_1          0x40
  54 #define QUEUE_LENGTH_2          0x80
  55 #define QUEUE_LENGTH_3          0xC0
  56 #define QUEUE_LENGTH_4          0
  57 #define CPU_TRANSFER_SIZE_32    0
  58 #define CPU_TRANSFER_SIZE_16    0x10
  59 #define CPU_TRANSFER_SIZE_8     0x20
  60 #define READ_ENDIANNESS_ABCD    0
  61 #define READ_ENDIANNESS_DCBA    0x4
  62 #define READ_ENDIANNESS_BADC    0x8
  63 #define READ_ENDIANNESS_CDAB    0xC
  64 #define WRITE_ENDIANNESS_ABCD   0
  65 #define WRITE_ENDIANNESS_DCBA   0x1
  66 #define WRITE_ENDIANNESS_BADC   0x2
  67 #define WRITE_ENDIANNESS_CDAB   0x3
  68
  69 /* various bits in configuration register EBI_CTRL_SIG_ACTLV */
  70 #define IORDY_ACTIVELEVEL_HIGH  (1 << 14)
  71 #define ALE_ACTIVELEVEL_HIGH    (1 <<  8)
  72
  73 /* bits in register EBI_SIG_LEVEL */
  74 #define IORDY_LEVEL_MASK        1
  75
  76 static inline void ebi_wait(void)
  77 {
  78         while (reg_read(EBI_STATUS(EBI_BASE)) & EXT_CPU_ACCESS_ACTIVE)
  79                 ;       /* wait */
  80 }
  81
  82 #endif