board/micronas/vct/vcth/reg_scc.h

   1 /*
   2  * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
   3  *
   4  * Copyright (C) 2006 Micronas GmbH
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef _REG_SCC_PREMIUM_H_
  10 #define _REG_SCC_PREMIUM_H_
  11
  12 #define SCC0_BASE               0x00110000
  13 #define SCC1_BASE               0x00110080
  14 #define SCC2_BASE               0x00110100
  15 #define SCC3_BASE               0x00110180
  16 #define SCC4_BASE               0x00110200
  17 #define SCC5_BASE               0x00110280
  18 #define SCC6_BASE               0x00110300
  19 #define SCC7_BASE               0x00110380
  20 #define SCC8_BASE               0x00110400
  21 #define SCC9_BASE               0x00110480
  22 #define SCC10_BASE              0x00110500
  23 #define SCC11_BASE              0x00110580
  24 #define SCC12_BASE              0x00110600
  25 #define SCC13_BASE              0x00110680
  26 #define SCC14_BASE              0x00110700
  27 #define SCC15_BASE              0x00110780
  28 #define SCC16_BASE              0x00110800
  29 #define SCC17_BASE              0x00110880
  30 #define SCC18_BASE              0x00110900
  31 #define SCC19_BASE              0x00110980
  32 #define SCC20_BASE              0x00110a00
  33 #define SCC21_BASE              0x00110a80
  34 #define SCC22_BASE              0x00110b00
  35 #define SCC23_BASE              0x00110b80
  36 #define SCC24_BASE              0x00110c00
  37 #define SCC25_BASE              0x00110c80
  38 #define SCC26_BASE              0x00110d00
  39 #define SCC27_BASE              0x00110d80
  40 #define SCC28_BASE              0x00110e00
  41 #define SCC29_BASE              0x00110e80
  42 #define SCC30_BASE              0x00110f00
  43 #define SCC31_BASE              0x00110f80
  44 #define SCC32_BASE              0x00111000
  45 #define SCC33_BASE              0x00111080
  46 #define SCC34_BASE              0x00111100
  47 #define SCC35_BASE              0x00111180
  48 #define SCC36_BASE              0x00111200
  49 #define SCC37_BASE              0x00111280
  50 #define SCC38_BASE              0x00111300
  51 #define SCC39_BASE              0x00111380
  52 #define SCC40_BASE              0x00111400
  53
  54 /*  Relative offsets of the register adresses */
  55
  56 #define SCC_ENABLE_OFFS         0x00000000
  57 #define SCC_ENABLE(base)        ((base) + SCC_ENABLE_OFFS)
  58 #define SCC_RESET_OFFS          0x00000004
  59 #define SCC_RESET(base)         ((base) + SCC_RESET_OFFS)
  60 #define SCC_VCID_OFFS           0x00000008
  61 #define SCC_VCID(base)          ((base) + SCC_VCID_OFFS)
  62 #define SCC_MCI_CFG_OFFS        0x0000000C
  63 #define SCC_MCI_CFG(base)       ((base) + SCC_MCI_CFG_OFFS)
  64 #define SCC_PACKET_CFG1_OFFS    0x00000010
  65 #define SCC_PACKET_CFG1(base)   ((base) + SCC_PACKET_CFG1_OFFS)
  66 #define SCC_PACKET_CFG2_OFFS    0x00000014
  67 #define SCC_PACKET_CFG2(base)   ((base) + SCC_PACKET_CFG2_OFFS)
  68 #define SCC_PACKET_CFG3_OFFS    0x00000018
  69 #define SCC_PACKET_CFG3(base)   ((base) + SCC_PACKET_CFG3_OFFS)
  70 #define SCC_DMA_CFG_OFFS        0x0000001C
  71 #define SCC_DMA_CFG(base)       ((base) + SCC_DMA_CFG_OFFS)
  72 #define SCC_CMD_OFFS            0x00000020
  73 #define SCC_CMD(base)           ((base) + SCC_CMD_OFFS)
  74 #define SCC_PRIO_OFFS           0x00000024
  75 #define SCC_PRIO(base)          ((base) + SCC_PRIO_OFFS)
  76 #define SCC_DEBUG_OFFS          0x00000028
  77 #define SCC_DEBUG(base)         ((base) + SCC_DEBUG_OFFS)
  78 #define SCC_STATUS_OFFS         0x0000002C
  79 #define SCC_STATUS(base)        ((base) + SCC_STATUS_OFFS)
  80 #define SCC_IMR_OFFS            0x00000030
  81 #define SCC_IMR(base)           ((base) + SCC_IMR_OFFS)
  82 #define SCC_ISR_OFFS            0x00000034
  83 #define SCC_ISR(base)           ((base) + SCC_ISR_OFFS)
  84 #define SCC_DMA_OFFSET_OFFS     0x00000038
  85 #define SCC_DMA_OFFSET(base)    ((base) + SCC_DMA_OFFSET_OFFS)
  86 #define SCC_RS_CTLSTS_OFFS      0x0000003C
  87 #define SCC_RS_CTLSTS(base)     ((base) + SCC_RS_CTLSTS_OFFS)
  88
  89 #endif