board/motionpro/motionpro.c

   1 /*
   2  * (C) Copyright 2003-2007
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * modified for Promess PRO - by Andy Joseph, andy@promessdev.com
   6  * modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com
   7  * modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3
   8  * Also changed the refresh for 100MHz operation
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <mpc5xxx.h>
  15 #include <miiphy.h>
  16 #include <libfdt.h>
  17
  18 #if defined(CONFIG_LED_STATUS)
  19 #include <status_led.h>
  20 #endif /* CONFIG_LED_STATUS */
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 /* Kollmorgen DPR initialization data */
  25 struct init_elem {
  26         unsigned long addr;
  27         unsigned len;
  28         char *data;
  29         } init_seq[] = {
  30                 {0x500003F2, 2, "\x86\x00"},            /* HW parameter */
  31                 {0x500003F0, 2, "\x00\x00"},
  32                 {0x500003EC, 4, "\x00\x80\xc1\x52"},    /* Magic word */
  33         };
  34
  35 /*
  36  * Initialize Kollmorgen DPR
  37  */
  38 static void kollmorgen_init(void)
  39 {
  40         unsigned i, j;
  41         vu_char *p;
  42
  43         for (i = 0; i < sizeof(init_seq) / sizeof(struct init_elem); ++i) {
  44                 p = (vu_char *)init_seq[i].addr;
  45                 for (j = 0; j < init_seq[i].len; ++j)
  46                         *(p + j) = *(init_seq[i].data + j);
  47         }
  48
  49         printf("DPR:   Kollmorgen DPR initialized\n");
  50 }
  51
  52
  53 /*
  54  * Early board initalization.
  55  */
  56 int board_early_init_r(void)
  57 {
  58         /* Now, when we are in RAM, disable Boot Chipselect and enable CS0 */
  59         *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25);
  60         *(vu_long *)MPC5XXX_ADDECR |= (1 << 16);
  61
  62         /* Initialize Kollmorgen DPR */
  63         kollmorgen_init();
  64
  65         return 0;
  66 }
  67
  68
  69 /*
  70  * Additional PHY intialization. After being reset in mpc5xxx_fec_init_phy(),
  71  * PHY goes into FX mode.  To take it out of the FX mode and switch into
  72  * desired TX operation, one needs to clear the FX_SEL bit of Mode Control
  73  * Register.
  74  */
  75 void reset_phy(void)
  76 {
  77         unsigned short mode_control;
  78
  79         miiphy_read("FEC", CONFIG_PHY_ADDR, 0x15, &mode_control);
  80         miiphy_write("FEC", CONFIG_PHY_ADDR, 0x15,
  81                         mode_control & 0xfffe);
  82         return;
  83 }
  84
  85 #ifndef CONFIG_SYS_RAMBOOT
  86 /*
  87  * Helper function to initialize SDRAM controller.
  88  */
  89 static void sdram_start(int hi_addr)
  90 {
  91         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  92
  93         /* unlock mode register */
  94         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
  95                                                 hi_addr_bit;
  96
  97         /* precharge all banks */
  98         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
  99                                                 hi_addr_bit;
 100
 101         /* auto refresh */
 102         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
 103                                                 hi_addr_bit;
 104
 105         /* auto refresh, second time */
 106         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
 107                                                 hi_addr_bit;
 108
 109         /* set mode register */
 110         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
 111
 112         /* normal operation */
 113         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
 114 }
 115 #endif /* !CONFIG_SYS_RAMBOOT */
 116
 117
 118 /*
 119  * Initalize SDRAM - configure SDRAM controller, detect memory size.
 120  */
 121 int initdram(void)
 122 {
 123         ulong dramsize = 0;
 124 #ifndef CONFIG_SYS_RAMBOOT
 125         ulong test1, test2;
 126
 127         /* According to AN3221 (MPC5200B SDRAM Initialization and
 128          * Configuration), the SDelay register must be written a value of
 129          * 0x00000004 as the first step of the SDRAM contorller configuration.
 130          */
 131         *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
 132
 133         /* configure SDRAM start/end for detection */
 134         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
 135         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
 136
 137         /* setup config registers */
 138         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 139         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 140
 141         sdram_start(0);
 142         test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 143         sdram_start(1);
 144         test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 145         if (test1 > test2) {
 146                 sdram_start(0);
 147                 dramsize = test1;
 148         } else {
 149                 dramsize = test2;
 150         }
 151
 152         /* memory smaller than 1MB is impossible */
 153         if (dramsize < (1 << 20))
 154                 dramsize = 0;
 155
 156         /* set SDRAM CS0 size according to the amount of RAM found */
 157         if (dramsize > 0) {
 158                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
 159                         __builtin_ffs(dramsize >> 20) - 1;
 160         } else {
 161                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 162         }
 163
 164         /* let SDRAM CS1 start right after CS0 and disable it */
 165         *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;
 166
 167 #else /* !CONFIG_SYS_RAMBOOT */
 168         /* retrieve size of memory connected to SDRAM CS0 */
 169         dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 170         if (dramsize >= 0x13)
 171                 dramsize = (1 << (dramsize - 0x13)) << 20;
 172         else
 173                 dramsize = 0;
 174 #endif /* CONFIG_SYS_RAMBOOT */
 175
 176         /* return total ram size */
 177         gd->ram_size = dramsize;
 178
 179         return 0;
 180 }
 181
 182
 183 int checkboard(void)
 184 {
 185         uchar rev = *(vu_char *)CPLD_REV_REGISTER;
 186         printf("Board: Promess Motion-PRO board (CPLD rev. 0x%02x)\n", rev);
 187         return 0;
 188 }
 189
 190
 191 #ifdef CONFIG_OF_BOARD_SETUP
 192 int ft_board_setup(void *blob, bd_t *bd)
 193 {
 194         ft_cpu_setup(blob, bd);
 195
 196         return 0;
 197 }
 198 #endif /* CONFIG_OF_BOARD_SETUP */
 199
 200
 201 #if defined(CONFIG_LED_STATUS)
 202 vu_long *regcode_to_regaddr(led_id_t regcode)
 203 {
 204         /* GPT Enable and Mode Select Register address */
 205         vu_long *reg_translate[] = {
 206                                         (vu_long *)MPC5XXX_GPT6_ENABLE,
 207                                         (vu_long *)MPC5XXX_GPT7_ENABLE,
 208                                    };
 209
 210         if (ARRAY_SIZE(reg_translate) <= regcode)
 211                 return NULL;
 212         return reg_translate[regcode];
 213 }
 214
 215 void __led_init(led_id_t regcode, int state)
 216 {
 217         vu_long *regaddr = regcode_to_regaddr(regcode);
 218
 219         *regaddr |= ENABLE_GPIO_OUT;
 220
 221         if (state == CONFIG_LED_STATUS_ON)
 222                 *((vu_long *) regaddr) |= LED_ON;
 223         else
 224                 *((vu_long *) regaddr) &= ~LED_ON;
 225 }
 226
 227 void __led_set(led_id_t regcode, int state)
 228 {
 229         vu_long *regaddr = regcode_to_regaddr(regcode);
 230
 231         if (state == CONFIG_LED_STATUS_ON)
 232                 *regaddr |= LED_ON;
 233         else
 234                 *regaddr &= ~LED_ON;
 235 }
 236
 237 void __led_toggle(led_id_t regcode)
 238 {
 239         vu_long *regaddr = regcode_to_regaddr(regcode);
 240
 241         *regaddr ^= LED_ON;
 242 }
 243 #endif /* CONFIG_LED_STATUS */