board/mpc8349ads/mpc8349ads.c

   1 /*
   2  * Copyright Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  *
  22  * Change log:
  23  * 20050101: Eran Liberty (liberty@freescale.com)
  24  *           Initial file creating (porting from 85XX & 8260)
  25  */
  26
  27 #include <common.h>
  28 #include <ioports.h>
  29 #include <mpc83xx.h>
  30 #include <asm/mpc8349_pci.h>
  31 #include <i2c.h>
  32 #include <spd.h>
  33 #include <miiphy.h>
  34 #if defined(CONFIG_PCI)
  35 #include <pci.h>
  36 #endif
  37 #if defined(CONFIG_SPD_EEPROM)
  38 #include <spd_sdram.h>
  39 #endif
  40 int fixed_sdram(void);
  41 void sdram_init(void);
  42
  43 int board_early_init_f (void)
  44 {
  45         volatile u8* bcsr = (volatile u8*)CFG_BCSR;
  46
  47         /* Enable flash write */
  48         bcsr[1] &= ~0x01;
  49
  50         return 0;
  51 }
  52
  53
  54 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
  55
  56 long int initdram (int board_type)
  57 {
  58         volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
  59         u32 msize = 0;
  60
  61         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  62                 return -1;
  63
  64         /* DDR SDRAM - Main SODIMM */
  65         im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
  66 #if defined(CONFIG_SPD_EEPROM)
  67         msize = spd_sdram(NULL);
  68 #else
  69         msize = fixed_sdram();
  70 #endif
  71         /*
  72          * Initialize SDRAM if it is on local bus.
  73          */
  74         sdram_init();
  75         puts("   DDR RAM: ");
  76         /* return total bus SDRAM size(bytes)  -- DDR */
  77         return (msize * 1024 * 1024);
  78 }
  79
  80
  81 #if !defined(CONFIG_SPD_EEPROM)
  82 /*************************************************************************
  83  *  fixed sdram init -- doesn't use serial presence detect.
  84  ************************************************************************/
  85 int fixed_sdram(void)
  86 {
  87         volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
  88         u32 msize = 0;
  89         u32 ddr_size;
  90         u32 ddr_size_log2;
  91
  92         msize = CFG_DDR_SIZE;
  93         for (ddr_size = msize << 20, ddr_size_log2 = 0;
  94              (ddr_size > 1);
  95              ddr_size = ddr_size>>1, ddr_size_log2++) {
  96                 if (ddr_size & 1) {
  97                         return -1;
  98                 }
  99         }
 100         im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 101 #if (CFG_DDR_SIZE != 256)
 102 #warning Currenly any ddr size other than 256 is not supported
 103 #endif
 104
 105         im->ddr.csbnds[0].csbnds = 0x00100017;
 106         im->ddr.csbnds[1].csbnds = 0x0018001f;
 107         im->ddr.csbnds[2].csbnds = 0x00000007;
 108         im->ddr.csbnds[3].csbnds = 0x0008000f;
 109         im->ddr.cs_config[0] = CFG_DDR_CONFIG;
 110         im->ddr.cs_config[1] = CFG_DDR_CONFIG;
 111         im->ddr.cs_config[2] = CFG_DDR_CONFIG;
 112         im->ddr.cs_config[3] = CFG_DDR_CONFIG;
 113         im->ddr.timing_cfg_1 =
 114                 3 << TIMING_CFG1_PRETOACT_SHIFT |
 115                 7 << TIMING_CFG1_ACTTOPRE_SHIFT |
 116                 3 << TIMING_CFG1_ACTTORW_SHIFT  |
 117                 4 << TIMING_CFG1_CASLAT_SHIFT   |
 118                 3 << TIMING_CFG1_REFREC_SHIFT   |
 119                 3 << TIMING_CFG1_WRREC_SHIFT    |
 120                 2 << TIMING_CFG1_ACTTOACT_SHIFT |
 121                 1 << TIMING_CFG1_WRTORD_SHIFT;
 122         im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT;
 123         im->ddr.sdram_cfg =
 124                 SDRAM_CFG_SREN
 125 #if defined(CONFIG_DDR_2T_TIMING)
 126                 | SDRAM_CFG_2T_EN
 127 #endif
 128                 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
 129         im->ddr.sdram_mode =
 130                 0x2000 << SDRAM_MODE_ESD_SHIFT |
 131                 0x0162 << SDRAM_MODE_SD_SHIFT;
 132
 133         im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT |
 134                 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT;
 135         udelay(200);
 136
 137         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 138
 139         return msize;
 140 }
 141 #endif/*!CFG_SPD_EEPROM*/
 142
 143
 144 int checkboard (void)
 145 {
 146         puts("Board: Freescale MPC8349ADS\n");
 147         return 0;
 148 }
 149
 150 /*
 151  * if MPC8349ADS is soldered with SDRAM
 152  */
 153 #if defined(CFG_BR2_PRELIM)  \
 154         && defined(CFG_OR2_PRELIM) \
 155         && defined(CFG_LBLAWBAR2_PRELIM) \
 156         && defined(CFG_LBLAWAR2_PRELIM)
 157 /*
 158  * Initialize SDRAM memory on the Local Bus.
 159  */
 160
 161 void
 162 sdram_init(void)
 163 {
 164         volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
 165         volatile lbus8349_t *lbc= &immap->lbus;
 166         uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 167
 168         puts("\n   SDRAM on Local Bus: ");
 169         print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 170
 171         /*
 172          * Setup SDRAM Base and Option Registers, already done in cpu_init.c
 173          */
 174
 175         /*setup mtrpt, lsrt and lbcr for LB bus*/
 176         lbc->lbcr = CFG_LBC_LBCR;
 177         lbc->mrtpr = CFG_LBC_MRTPR;
 178         lbc->lsrt = CFG_LBC_LSRT;
 179         asm("sync");
 180
 181         /*
 182          * Configure the SDRAM controller Machine Mode Register.
 183          */
 184         lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation*/
 185
 186         lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733;precharge all the banks*/
 187         asm("sync");
 188         *sdram_addr = 0xff;
 189         udelay(100);
 190
 191         lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/
 192         asm("sync");
 193         /*1 times*/
 194         *sdram_addr = 0xff;
 195         udelay(100);
 196         /*2 times*/
 197         *sdram_addr = 0xff;
 198         udelay(100);
 199         /*3 times*/
 200         *sdram_addr = 0xff;
 201         udelay(100);
 202         /*4 times*/
 203         *sdram_addr = 0xff;
 204         udelay(100);
 205         /*5 times*/
 206         *sdram_addr = 0xff;
 207         udelay(100);
 208         /*6 times*/
 209         *sdram_addr = 0xff;
 210         udelay(100);
 211         /*7 times*/
 212         *sdram_addr = 0xff;
 213         udelay(100);
 214         /*8 times*/
 215         *sdram_addr = 0xff;
 216         udelay(100);
 217
 218         /* 0x58636733;mode register write operation */
 219         lbc->lsdmr = CFG_LBC_LSDMR_4;
 220         asm("sync");
 221         *sdram_addr = 0xff;
 222         udelay(100);
 223
 224         lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation*/
 225         asm("sync");
 226         *sdram_addr = 0xff;
 227         udelay(100);
 228 }
 229 #else
 230 void
 231 sdram_init(void)
 232 {
 233         put("SDRAM on Local Bus is NOT available!\n");
 234 }
 235 #endif