2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/global_data.h>
30 #include <asm/mpc8349_pci.h>
32 #if defined(CONFIG_OF_FLAT_TREE)
36 DECLARE_GLOBAL_DATA_PTR
;
38 /* System RAM mapped to PCI space */
39 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
40 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
42 #ifndef CONFIG_PCI_PNP
43 static struct pci_config_table pci_mpc8349itx_config_table
[] = {
51 pci_cfgfunc_config_device
,
55 PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
}
61 static struct pci_controller pci_hose
[] = {
63 #ifndef CONFIG_PCI_PNP
64 config_table
:pci_mpc8349itx_config_table
,
68 #ifndef CONFIG_PCI_PNP
69 config_table
:pci_mpc8349itx_config_table
,
74 /**************************************************************************
77 * NOTICE: PCI2 is not currently supported
80 void pci_init_board(void)
82 volatile immap_t
*immr
;
83 volatile clk83xx_t
*clk
;
84 volatile law83xx_t
*pci_law
;
85 volatile pot83xx_t
*pci_pot
;
86 volatile pcictrl83xx_t
*pci_ctrl
;
87 volatile pciconf83xx_t
*pci_conf
;
92 struct pci_controller
*hose
;
94 immr
= (immap_t
*) CFG_IMMR
;
95 clk
= (clk83xx_t
*) & immr
->clk
;
96 pci_law
= immr
->sysconf
.pcilaw
;
97 pci_pot
= immr
->ios
.pot
;
98 pci_ctrl
= immr
->pci_ctrl
;
99 pci_conf
= immr
->pci_conf
;
104 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
110 #ifdef CONFIG_HARD_I2C
112 /* Read the PCI_M66EN jumper setting */
113 if ((i2c_read(CFG_I2C_8574_ADDR2
, 0, 0, ®8
, sizeof(reg8
)) == 0) ||
114 (i2c_read(CFG_I2C_8574A_ADDR2
, 0, 0, ®8
, sizeof(reg8
)) == 0)) {
115 if (reg8
& I2C_8574_PCI66
)
116 clk
->occr
= 0xff000000; /* 66 MHz PCI */
118 clk
->occr
= 0xff600001; /* 33 MHz PCI */
120 clk
->occr
= 0xff600001; /* 33 MHz PCI */
123 clk
->occr
= 0xff000000; /* 66 MHz PCI */
129 * Release PCI RST Output signal
135 #ifdef CONFIG_MPC83XX_PCI2
141 /* We need to wait at least a 1sec based on PCI specs */
145 for (i
= 0; i
< 1000; i
++)
150 * Configure PCI Local Access Windows
152 pci_law
[0].bar
= CFG_PCI1_MEM_PHYS
& LAWBAR_BAR
;
153 pci_law
[0].ar
= LAWAR_EN
| LAWAR_SIZE_1G
;
155 pci_law
[1].bar
= CFG_PCI1_IO_PHYS
& LAWBAR_BAR
;
156 pci_law
[1].ar
= LAWAR_EN
| LAWAR_SIZE_32M
;
159 * Configure PCI Outbound Translation Windows
162 /* PCI1 mem space - prefetch */
163 pci_pot
[0].potar
= (CFG_PCI1_MEM_BASE
>> 12) & POTAR_TA_MASK
;
164 pci_pot
[0].pobar
= (CFG_PCI1_MEM_PHYS
>> 12) & POBAR_BA_MASK
;
165 pci_pot
[0].pocmr
= POCMR_EN
| POCMR_PREFETCH_EN
| POCMR_CM_256M
;
168 pci_pot
[1].potar
= (CFG_PCI1_IO_BASE
>> 12) & POTAR_TA_MASK
;
169 pci_pot
[1].pobar
= (CFG_PCI1_IO_PHYS
>> 12) & POBAR_BA_MASK
;
170 pci_pot
[1].pocmr
= POCMR_EN
| POCMR_IO
| POCMR_CM_16M
;
172 /* PCI1 mmio - non-prefetch mem space */
173 pci_pot
[2].potar
= (CFG_PCI1_MMIO_BASE
>> 12) & POTAR_TA_MASK
;
174 pci_pot
[2].pobar
= (CFG_PCI1_MMIO_PHYS
>> 12) & POBAR_BA_MASK
;
175 pci_pot
[2].pocmr
= POCMR_EN
| POCMR_CM_256M
;
178 * Configure PCI Inbound Translation Windows
181 /* we need RAM mapped to PCI space for the devices to
182 * access main memory */
183 pci_ctrl
[0].pitar1
= 0x0;
184 pci_ctrl
[0].pibar1
= 0x0;
185 pci_ctrl
[0].piebar1
= 0x0;
186 pci_ctrl
[0].piwar1
= PIWAR_EN
| PIWAR_PF
| PIWAR_RTT_SNOOP
|
187 PIWAR_WTT_SNOOP
| (__ilog2(gd
->ram_size
) - 1);
189 hose
->first_busno
= 0;
190 hose
->last_busno
= 0xff;
192 /* PCI memory prefetch space */
193 pci_set_region(hose
->regions
+ 0,
196 CFG_PCI1_MEM_SIZE
, PCI_REGION_MEM
| PCI_REGION_PREFETCH
);
198 /* PCI memory space */
199 pci_set_region(hose
->regions
+ 1,
201 CFG_PCI1_MMIO_PHYS
, CFG_PCI1_MMIO_SIZE
, PCI_REGION_MEM
);
204 pci_set_region(hose
->regions
+ 2,
206 CFG_PCI1_IO_PHYS
, CFG_PCI1_IO_SIZE
, PCI_REGION_IO
);
208 /* System memory space */
209 pci_set_region(hose
->regions
+ 3,
210 CONFIG_PCI_SYS_MEM_BUS
,
211 CONFIG_PCI_SYS_MEM_PHYS
,
212 gd
->ram_size
, PCI_REGION_MEM
| PCI_REGION_MEMORY
);
214 hose
->region_count
= 4;
216 pci_setup_indirect(hose
,
217 (CFG_IMMR
+ 0x8300), (CFG_IMMR
+ 0x8304));
219 pci_register_hose(hose
);
222 * Write to Command register
225 dev
= PCI_BDF(hose
->first_busno
, 0, 0);
226 pci_hose_read_config_word(hose
, dev
, PCI_COMMAND
, ®16
);
227 reg16
|= PCI_COMMAND_SERR
| PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
;
228 pci_hose_write_config_word(hose
, dev
, PCI_COMMAND
, reg16
);
231 * Clear non-reserved bits in status register.
233 pci_hose_write_config_word(hose
, dev
, PCI_STATUS
, 0xffff);
234 pci_hose_write_config_byte(hose
, dev
, PCI_LATENCY_TIMER
, 0x80);
235 pci_hose_write_config_byte(hose
, dev
, PCI_CACHE_LINE_SIZE
, 0x08);
237 #ifdef CONFIG_PCI_SCAN_SHOW
238 printf("PCI: Bus Dev VenId DevId Class Int\n");
243 hose
->last_busno
= pci_hose_scan(hose
);
245 #ifdef CONFIG_MPC83XX_PCI2
249 * Configure PCI Outbound Translation Windows
252 /* PCI2 mem space - prefetch */
253 pci_pot
[3].potar
= (CFG_PCI2_MEM_BASE
>> 12) & POTAR_TA_MASK
;
254 pci_pot
[3].pobar
= (CFG_PCI2_MEM_PHYS
>> 12) & POBAR_BA_MASK
;
255 pci_pot
[3].pocmr
= POCMR_EN
| POCMR_PCI2
| POCMR_PREFETCH_EN
| POCMR_CM_256M
;
258 pci_pot
[4].potar
= (CFG_PCI2_IO_BASE
>> 12) & POTAR_TA_MASK
;
259 pci_pot
[4].pobar
= (CFG_PCI2_IO_PHYS
>> 12) & POBAR_BA_MASK
;
260 pci_pot
[4].pocmr
= POCMR_EN
| POCMR_PCI2
| POCMR_IO
| POCMR_CM_16M
;
262 /* PCI2 mmio - non-prefetch mem space */
263 pci_pot
[5].potar
= (CFG_PCI2_MMIO_BASE
>> 12) & POTAR_TA_MASK
;
264 pci_pot
[5].pobar
= (CFG_PCI2_MMIO_PHYS
>> 12) & POBAR_BA_MASK
;
265 pci_pot
[5].pocmr
= POCMR_EN
| POCMR_PCI2
| POCMR_CM_256M
;
268 * Configure PCI Inbound Translation Windows
271 /* we need RAM mapped to PCI space for the devices to
272 * access main memory */
273 pci_ctrl
[1].pitar1
= 0x0;
274 pci_ctrl
[1].pibar1
= 0x0;
275 pci_ctrl
[1].piebar1
= 0x0;
277 PIWAR_EN
| PIWAR_PF
| PIWAR_RTT_SNOOP
| PIWAR_WTT_SNOOP
|
278 (__ilog2(gd
->ram_size
) - 1);
280 hose
->first_busno
= pci_hose
[0].last_busno
+ 1;
281 hose
->last_busno
= 0xff;
283 /* PCI memory prefetch space */
284 pci_set_region(hose
->regions
+ 0,
287 CFG_PCI2_MEM_SIZE
, PCI_REGION_MEM
| PCI_REGION_PREFETCH
);
289 /* PCI memory space */
290 pci_set_region(hose
->regions
+ 1,
292 CFG_PCI2_MMIO_PHYS
, CFG_PCI2_MMIO_SIZE
, PCI_REGION_MEM
);
295 pci_set_region(hose
->regions
+ 2,
297 CFG_PCI2_IO_PHYS
, CFG_PCI2_IO_SIZE
, PCI_REGION_IO
);
299 /* System memory space */
300 pci_set_region(hose
->regions
+ 3,
301 CONFIG_PCI_SYS_MEM_BUS
,
302 CONFIG_PCI_SYS_MEM_PHYS
,
303 gd
->ram_size
, PCI_REGION_MEM
| PCI_REGION_MEMORY
);
305 hose
->region_count
= 4;
307 pci_setup_indirect(hose
,
308 (CFG_IMMR
+ 0x8380), (CFG_IMMR
+ 0x8384));
310 pci_register_hose(hose
);
313 * Write to Command register
316 dev
= PCI_BDF(hose
->first_busno
, 0, 0);
317 pci_hose_read_config_word(hose
, dev
, PCI_COMMAND
, ®16
);
318 reg16
|= PCI_COMMAND_SERR
| PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
;
319 pci_hose_write_config_word(hose
, dev
, PCI_COMMAND
, reg16
);
322 * Clear non-reserved bits in status register.
324 pci_hose_write_config_word(hose
, dev
, PCI_STATUS
, 0xffff);
325 pci_hose_write_config_byte(hose
, dev
, PCI_LATENCY_TIMER
, 0x80);
326 pci_hose_write_config_byte(hose
, dev
, PCI_CACHE_LINE_SIZE
, 0x08);
331 hose
->last_busno
= pci_hose_scan(hose
);
335 #endif /* CONFIG_PCI */
336 #ifdef CONFIG_OF_FLAT_TREE
338 ft_pci_setup(void *blob
, bd_t
*bd
)
343 p
= (u32
*)ft_get_prop(blob
, "/" OF_SOC
"/pci@8500/bus-range", &len
);
345 p
[0] = pci_hose
[0].first_busno
;
346 p
[1] = pci_hose
[0].last_busno
;
349 #ifdef CONFIG_MPC83XX_PCI2
350 p
= (u32
*)ft_get_prop(blob
, "/" OF_SOC
"/pci@8600/bus-range", &len
);
352 p
[0] = pci_hose
[1].first_busno
;
353 p
[1] = pci_hose
[1].last_busno
;
357 #endif /* CONFIG_OF_FLAT_TREE */