board/mpl/mip405/init.S

   1 /*
   2  * SPDX-License-Identifier:     GPL-2.0 ibm-pibs
   3  */
   4 /*-----------------------------------------------------------------------------
   5  * Function:     ext_bus_cntlr_init
   6  * Description:  Initializes the External Bus Controller for the external
   7  *              peripherals. IMPORTANT: For pass1 this code must run from
   8  *              cache since you can not reliably change a peripheral banks
   9  *              timing register (pbxap) while running code from that bank.
  10  *              For ex., since we are running from ROM on bank 0, we can NOT
  11  *              execute the code that modifies bank 0 timings from ROM, so
  12  *              we run it from cache.
  13  *      Bank 0 - Flash or Multi Purpose Socket
  14  *      Bank 1 - Multi Purpose Socket or Flash (set in C-Code)
  15  *      Bank 2 - UART 1 (set in C-Code)
  16  *      Bank 3 - UART 2 (set in C-Code)
  17  *      Bank 4 - not used
  18  *      Bank 5 - not used
  19  *      Bank 6 - not used
  20  *      Bank 7 - PLD Register
  21  *-----------------------------------------------------------------------------*/
  22 #define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
  23
  24 #include <configs/MIP405.h>
  25 #include <ppc_asm.tmpl>
  26 #include <ppc_defs.h>
  27
  28 #include <asm/cache.h>
  29 #include <asm/mmu.h>
  30 #include <asm/ppc4xx.h>
  31 #include "mip405.h"
  32
  33
  34   .globl ext_bus_cntlr_init
  35 ext_bus_cntlr_init:
  36   mflr   r4                      /* save link register */
  37   mfdcr  r3,CPC0_PSR                /* get strapping reg */
  38   andi.  r0, r3, PSR_ROM_LOC     /* mask out irrelevant bits */
  39   bnelr                          /* jump back if PCI boot */
  40
  41   bl      ..getAddr
  42 ..getAddr:
  43   mflr    r3                      /* get address of ..getAddr */
  44   mtlr    r4                      /* restore link register */
  45   addi    r4,0,14                 /* set ctr to 14; used to prefetch */
  46   mtctr   r4                      /* 14 cache lines to fit this function */
  47                                    /* in cache (gives us 8x14=112 instrctns) */
  48 ..ebcloop:
  49   icbt    r0,r3                   /* prefetch cache line for addr in r3 */
  50   addi    r3,r3,32                                                              /* move to next cache line */
  51   bdnz    ..ebcloop               /* continue for 14 cache lines */
  52
  53    /*-------------------------------------------------------------------
  54     * Delay to ensure all accesses to ROM are complete before changing
  55     * bank 0 timings.
  56     *------------------------------------------------------------------- */
  57         addis   r3,0,0x0
  58   ori     r3,r3,0xA000
  59   mtctr   r3
  60 ..spinlp:
  61   bdnz    ..spinlp                /* spin loop */
  62
  63         /*-----------------------------------------------------------------------
  64          * decide boot up mode
  65          *----------------------------------------------------------------------- */
  66         addi            r4,0,PB0CR
  67         mtdcr           EBC0_CFGADDR,r4
  68         mfdcr           r4,EBC0_CFGDATA
  69
  70         andi.           r0, r4, 0x2000                  /* mask out irrelevant bits */
  71         beq             0f                              /* jump if 8 bit bus width */
  72
  73         /* setup 16 bit things
  74    *-----------------------------------------------------------------------
  75    * Memory Bank 0 (16 Bit Flash) initialization
  76    *---------------------------------------------------------------------- */
  77
  78         addi    r4,0,PB1AP
  79         mtdcr   EBC0_CFGADDR,r4
  80         addis   r4,0,(FLASH_AP_B)@h
  81         ori     r4,r4,(FLASH_AP_B)@l
  82         mtdcr   EBC0_CFGDATA,r4
  83
  84         addi    r4,0,PB0CR
  85         mtdcr   EBC0_CFGADDR,r4
  86         /* BS=0x010(4MB),BU=0x3(R/W), */
  87         addis   r4,0,(FLASH_CR_B)@h
  88         ori     r4,r4,(FLASH_CR_B)@l
  89         mtdcr   EBC0_CFGDATA,r4
  90         b                               1f
  91
  92 0:
  93
  94         /* 8Bit boot mode: */
  95         /*-----------------------------------------------------------------------
  96         * Memory Bank 0 Multi Purpose Socket initialization
  97         *----------------------------------------------------------------------- */
  98         /* 0x7F8FFE80 slowest boot */
  99         addi    r4,0,PB1AP
 100         mtdcr   EBC0_CFGADDR,r4
 101         addis   r4,0,(MPS_AP_B)@h
 102         ori     r4,r4,(MPS_AP_B)@l
 103         mtdcr   EBC0_CFGDATA,r4
 104
 105         addi    r4,0,PB0CR
 106         mtdcr   EBC0_CFGADDR,r4
 107         /* BS=0x010(4MB),BU=0x3(R/W), */
 108         addis   r4,0,(MPS_CR_B)@h
 109         ori     r4,r4,(MPS_CR_B)@l
 110
 111         mtdcr   EBC0_CFGDATA,r4
 112
 113
 114 1:
 115   /*-----------------------------------------------------------------------
 116    * Memory Bank 2-3-4-5-6 (not used) initialization
 117    *-----------------------------------------------------------------------*/
 118   addi    r4,0,PB1CR
 119   mtdcr   EBC0_CFGADDR,r4
 120   addis   r4,0,0x0000
 121   ori     r4,r4,0x0000
 122   mtdcr   EBC0_CFGDATA,r4
 123
 124   addi    r4,0,PB2CR
 125   mtdcr   EBC0_CFGADDR,r4
 126   addis   r4,0,0x0000
 127   ori     r4,r4,0x0000
 128   mtdcr   EBC0_CFGDATA,r4
 129
 130   addi    r4,0,PB3CR
 131   mtdcr   EBC0_CFGADDR,r4
 132   addis   r4,0,0x0000
 133   ori     r4,r4,0x0000
 134   mtdcr   EBC0_CFGDATA,r4
 135
 136   addi    r4,0,PB4CR
 137   mtdcr   EBC0_CFGADDR,r4
 138   addis   r4,0,0x0000
 139   ori     r4,r4,0x0000
 140   mtdcr   EBC0_CFGDATA,r4
 141
 142   addi    r4,0,PB5CR
 143   mtdcr   EBC0_CFGADDR,r4
 144   addis   r4,0,0x0000
 145   ori     r4,r4,0x0000
 146   mtdcr   EBC0_CFGDATA,r4
 147
 148   addi    r4,0,PB6CR
 149   mtdcr   EBC0_CFGADDR,r4
 150   addis   r4,0,0x0000
 151   ori     r4,r4,0x0000
 152   mtdcr   EBC0_CFGDATA,r4
 153
 154   addi    r4,0,PB7CR
 155   mtdcr   EBC0_CFGADDR,r4
 156   addis   r4,0,0x0000
 157   ori     r4,r4,0x0000
 158   mtdcr   EBC0_CFGDATA,r4
 159   nop                           /* pass2 DCR errata #8 */
 160   blr
 161
 162 #if defined(CONFIG_BOOT_PCI)
 163     .section .bootpg,"ax"
 164     .globl _start_pci
 165 /*******************************************
 166  */
 167
 168 _start_pci:
 169   /* first handle errata #68 / PCI_18 */
 170   iccci   r0, r0          /* invalidate I-cache */
 171   lis     r31, 0
 172   mticcr  r31             /* ICCR = 0 (all uncachable) */
 173   isync
 174
 175   mfccr0  r28             /* set CCR0[24] = 1 */
 176   ori     r28, r28, 0x0080
 177   mtccr0  r28
 178
 179   /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
 180   lis     r28, 0xEF40
 181   addi    r28, r28, 0x0004
 182   stw     r31, 0x0C(r28)  /* clear PMM0PCIHA */
 183   lis     r29, 0xFFF8     /* open 512 kByte */
 184   addi    r29, r29, 0x0001/* and enable this region */
 185   stwbrx  r29, r0, r28    /* write PMM0MA */
 186
 187   lis     r28, 0xEEC0     /* address of PCIC0_CFGADDR */
 188   addi    r29, r28, 4     /* add 4 to r29 -> PCIC0_CFGDATA */
 189
 190   lis     r31, 0x8000     /* set en bit bus 0 */
 191   ori     r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
 192   stwbrx  r31, r0, r28    /* write it */
 193
 194   lwbrx   r31, r0, r29    /* load XBCS register */
 195   oris    r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
 196   stwbrx  r31, r0, r29    /* write back XBCS register */
 197
 198   nop
 199   nop
 200   b     _start          /* normal start */
 201 #endif