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1 /*
2 * (C) Copyright 2001
3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 *
24 * TODO: clean-up
25 */
26
27 /*
28 * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
29 *
30 * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
31 * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
32 * parameters from the datasheet are:
33 * Tclk = 7.5ns (CL = 2)
34 * Trp = 15ns
35 * Trc = 60ns
36 * Trcd = 15ns
37 * Trfc = 66ns
38 *
39 * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
40 * period is 10ns and the parameters needed for the Timing Register are:
41 * CASL = CL = 2 clock cycles
42 * PTA = Trp = 15ns / 10ns = 2 clock cycles
43 * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
44 * LDF = 2 clock cycles (but can be extended to meet board-level timing)
45 * RFTA = Trfc = 66ns / 10ns= 7 clock cycles
46 * RCD = Trcd = 15ns / 10ns= 2 clock cycles
47 *
48 * The actual bit settings in the register would be:
49 *
50 * CASL = 0b01
51 * PTA = 0b01
52 * CTP = 0b10
53 * LDF = 0b01
54 * RFTA = 0b011
55 * RCD = 0b01
56 *
57 * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
58 * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
59 * defined as Trc rather than Trfc.
60 * When using DIMM modules, most but not all of the required timing parameters can be read
61 * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
62 * are not available from the EEPROM
63 */
64
65 #include <common.h>
66 #include "mip405.h"
67 #include <asm/processor.h>
68 #include <405gp_i2c.h>
69 #include <miiphy.h>
70 #include "../common/common_util.h"
71 #include <i2c.h>
72 #include <rtc.h>
73 extern block_dev_desc_t * scsi_get_dev(int dev);
74 extern block_dev_desc_t * ide_get_dev(int dev);
75
76 #undef SDRAM_DEBUG
77 #define ENABLE_ECC /* for ecc boards */
78 #define FALSE 0
79 #define TRUE 1
80
81 /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
82 #ifndef __ldiv_t_defined
83 typedef struct {
84 long int quot; /* Quotient */
85 long int rem; /* Remainder */
86 } ldiv_t;
87 extern ldiv_t ldiv (long int __numer, long int __denom);
88 # define __ldiv_t_defined 1
89 #endif
90
91
92 #define PLD_PART_REG PER_PLD_ADDR + 0
93 #define PLD_VERS_REG PER_PLD_ADDR + 1
94 #define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
95 #define PLD_IRQ_REG PER_PLD_ADDR + 3
96 #define PLD_COM_MODE_REG PER_PLD_ADDR + 4
97 #define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
98
99 #define MEGA_BYTE (1024*1024)
100
101 typedef struct {
102 unsigned char boardtype; /* Board revision and Population Options */
103 unsigned char cal; /* cas Latency (will be programmend as cal-1) */
104 unsigned char trp; /* datain27 in clocks */
105 unsigned char trcd; /* datain29 in clocks */
106 unsigned char tras; /* datain30 in clocks */
107 unsigned char tctp; /* tras - trcd in clocks */
108 unsigned char am; /* Address Mod (will be programmed as am-1) */
109 unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
110 unsigned char ecc; /* if true, ecc is enabled */
111 } sdram_t;
112 #if defined(CONFIG_MIP405T)
113 const sdram_t sdram_table[] = {
114 { 0x0F, /* MIP405T Rev A, 64MByte -1 Board */
115 3, /* Case Latenty = 3 */
116 3, /* trp 20ns / 7.5 ns datain[27] */
117 3, /* trcd 20ns /7.5 ns (datain[29]) */
118 6, /* tras 44ns /7.5 ns (datain[30]) */
119 4, /* tcpt 44 - 20ns = 24ns */
120 2, /* Address Mode = 2 (12x9x4) */
121 3, /* size value (32MByte) */
122 0}, /* ECC disabled */
123 { 0xff, /* terminator */
124 0xff,
125 0xff,
126 0xff,
127 0xff,
128 0xff,
129 0xff,
130 0xff }
131 };
132 #else
133 const sdram_t sdram_table[] = {
134 { 0x0f, /* Rev A, 128MByte -1 Board */
135 3, /* Case Latenty = 3 */
136 3, /* trp 20ns / 7.5 ns datain[27] */
137 3, /* trcd 20ns /7.5 ns (datain[29]) */
138 6, /* tras 44ns /7.5 ns (datain[30]) */
139 4, /* tcpt 44 - 20ns = 24ns */
140 3, /* Address Mode = 3 */
141 5, /* size value */
142 1}, /* ECC enabled */
143 { 0x07, /* Rev A, 64MByte -2 Board */
144 3, /* Case Latenty = 3 */
145 3, /* trp 20ns / 7.5 ns datain[27] */
146 3, /* trcd 20ns /7.5 ns (datain[29]) */
147 6, /* tras 44ns /7.5 ns (datain[30]) */
148 4, /* tcpt 44 - 20ns = 24ns */
149 2, /* Address Mode = 2 */
150 4, /* size value */
151 1}, /* ECC enabled */
152 { 0x03, /* Rev A, 128MByte -4 Board */
153 3, /* Case Latenty = 3 */
154 3, /* trp 20ns / 7.5 ns datain[27] */
155 3, /* trcd 20ns /7.5 ns (datain[29]) */
156 6, /* tras 44ns /7.5 ns (datain[30]) */
157 4, /* tcpt 44 - 20ns = 24ns */
158 3, /* Address Mode = 3 */
159 5, /* size value */
160 1}, /* ECC enabled */
161 { 0x1f, /* Rev B, 128MByte -3 Board */
162 3, /* Case Latenty = 3 */
163 3, /* trp 20ns / 7.5 ns datain[27] */
164 3, /* trcd 20ns /7.5 ns (datain[29]) */
165 6, /* tras 44ns /7.5 ns (datain[30]) */
166 4, /* tcpt 44 - 20ns = 24ns */
167 3, /* Address Mode = 3 */
168 5, /* size value */
169 1}, /* ECC enabled */
170 { 0x2f, /* Rev C, 128MByte -3 Board */
171 3, /* Case Latenty = 3 */
172 3, /* trp 20ns / 7.5 ns datain[27] */
173 3, /* trcd 20ns /7.5 ns (datain[29]) */
174 6, /* tras 44ns /7.5 ns (datain[30]) */
175 4, /* tcpt 44 - 20ns = 24ns */
176 3, /* Address Mode = 3 */
177 5, /* size value */
178 1}, /* ECC enabled */
179 { 0xff, /* terminator */
180 0xff,
181 0xff,
182 0xff,
183 0xff,
184 0xff,
185 0xff,
186 0xff }
187 };
188 #endif /*CONFIG_MIP405T */
189 void SDRAM_err (const char *s)
190 {
191 #ifndef SDRAM_DEBUG
192 DECLARE_GLOBAL_DATA_PTR;
193
194 (void) get_clocks ();
195 gd->baudrate = 9600;
196 serial_init ();
197 #endif
198 serial_puts ("\n");
199 serial_puts (s);
200 serial_puts ("\n enable SDRAM_DEBUG for more info\n");
201 for (;;);
202 }
203
204
205 unsigned char get_board_revcfg (void)
206 {
207 out8 (PER_BOARD_ADDR, 0);
208 return (in8 (PER_BOARD_ADDR));
209 }
210
211
212 #ifdef SDRAM_DEBUG
213
214 void write_hex (unsigned char i)
215 {
216 char cc;
217
218 cc = i >> 4;
219 cc &= 0xf;
220 if (cc > 9)
221 serial_putc (cc + 55);
222 else
223 serial_putc (cc + 48);
224 cc = i & 0xf;
225 if (cc > 9)
226 serial_putc (cc + 55);
227 else
228 serial_putc (cc + 48);
229 }
230
231 void write_4hex (unsigned long val)
232 {
233 write_hex ((unsigned char) (val >> 24));
234 write_hex ((unsigned char) (val >> 16));
235 write_hex ((unsigned char) (val >> 8));
236 write_hex ((unsigned char) val);
237 }
238
239 #endif
240
241
242 int init_sdram (void)
243 {
244 DECLARE_GLOBAL_DATA_PTR;
245
246 unsigned long tmp, baseaddr;
247 unsigned short i;
248 unsigned char trp_clocks,
249 trcd_clocks,
250 tras_clocks,
251 trc_clocks,
252 tctp_clocks;
253 unsigned char cal_val;
254 unsigned char bc;
255 unsigned long sdram_tim, sdram_bank;
256
257 /*i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);*/
258 (void) get_clocks ();
259 gd->baudrate = 9600;
260 serial_init ();
261 /* set up the pld */
262 mtdcr (ebccfga, pb7ap);
263 mtdcr (ebccfgd, PLD_AP);
264 mtdcr (ebccfga, pb7cr);
265 mtdcr (ebccfgd, PLD_CR);
266 /* THIS IS OBSOLETE */
267 /* set up the board rev reg*/
268 mtdcr (ebccfga, pb5ap);
269 mtdcr (ebccfgd, BOARD_AP);
270 mtdcr (ebccfga, pb5cr);
271 mtdcr (ebccfgd, BOARD_CR);
272 #ifdef SDRAM_DEBUG
273 /* get all informations from PLD */
274 serial_puts ("\nPLD Part 0x");
275 bc = in8 (PLD_PART_REG);
276 write_hex (bc);
277 serial_puts ("\nPLD Vers 0x");
278 bc = in8 (PLD_VERS_REG);
279 write_hex (bc);
280 serial_puts ("\nBoard Rev 0x");
281 bc = in8 (PLD_BOARD_CFG_REG);
282 write_hex (bc);
283 serial_puts ("\n");
284 #endif
285 /* check board */
286 bc = in8 (PLD_PART_REG);
287 #if defined(CONFIG_MIP405T)
288 if((bc & 0x80)==0)
289 SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");
290 #else
291 if((bc & 0x80)==0x80)
292 SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
293 #endif
294 /* set-up the chipselect machine */
295 mtdcr (ebccfga, pb0cr); /* get cs0 config reg */
296 tmp = mfdcr (ebccfgd);
297 if ((tmp & 0x00002000) == 0) {
298 /* MPS Boot, set up the flash */
299 mtdcr (ebccfga, pb1ap);
300 mtdcr (ebccfgd, FLASH_AP);
301 mtdcr (ebccfga, pb1cr);
302 mtdcr (ebccfgd, FLASH_CR);
303 } else {
304 /* Flash boot, set up the MPS */
305 mtdcr (ebccfga, pb1ap);
306 mtdcr (ebccfgd, MPS_AP);
307 mtdcr (ebccfga, pb1cr);
308 mtdcr (ebccfgd, MPS_CR);
309 }
310 /* set up UART0 (CS2) and UART1 (CS3) */
311 mtdcr (ebccfga, pb2ap);
312 mtdcr (ebccfgd, UART0_AP);
313 mtdcr (ebccfga, pb2cr);
314 mtdcr (ebccfgd, UART0_CR);
315 mtdcr (ebccfga, pb3ap);
316 mtdcr (ebccfgd, UART1_AP);
317 mtdcr (ebccfga, pb3cr);
318 mtdcr (ebccfgd, UART1_CR);
319 bc = in8 (PLD_BOARD_CFG_REG);
320 #ifdef SDRAM_DEBUG
321 serial_puts ("\nstart SDRAM Setup\n");
322 serial_puts ("\nBoard Rev: ");
323 write_hex (bc);
324 serial_puts ("\n");
325 #endif
326 i = 0;
327 baseaddr = CFG_SDRAM_BASE;
328 while (sdram_table[i].sz != 0xff) {
329 if (sdram_table[i].boardtype == bc)
330 break;
331 i++;
332 }
333 if (sdram_table[i].boardtype != bc)
334 SDRAM_err ("No SDRAM table found for this board!!!\n");
335 #ifdef SDRAM_DEBUG
336 serial_puts (" found table ");
337 write_hex (i);
338 serial_puts (" \n");
339 #endif
340 /* since the ECC initialisation needs some time,
341 * we show that we're alive
342 */
343 if (sdram_table[i].ecc)
344 serial_puts ("\nInitializing SDRAM, Please stand by");
345 cal_val = sdram_table[i].cal - 1; /* Cas Latency */
346 trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */
347 trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */
348 tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */
349 /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
350 tctp_clocks = sdram_table[i].tctp; /* 44 - 20ns = 24ns */
351 /* trc_clocks is sum of trp_clocks + tras_clocks */
352 trc_clocks = trp_clocks + tras_clocks;
353 /* get SDRAM timing register */
354 mtdcr (memcfga, mem_sdtr1);
355 sdram_tim = mfdcr (memcfgd) & ~0x018FC01F;
356 /* insert CASL value */
357 sdram_tim |= ((unsigned long) (cal_val)) << 23;
358 /* insert PTA value */
359 sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;
360 /* insert CTP value */
361 sdram_tim |=
362 ((unsigned long) (trc_clocks - trp_clocks -
363 trcd_clocks)) << 16;
364 /* insert LDF (always 01) */
365 sdram_tim |= ((unsigned long) 0x01) << 14;
366 /* insert RFTA value */
367 sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;
368 /* insert RCD value */
369 sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;
370
371 tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */
372 /* insert SZ value; */
373 tmp |= ((unsigned long) sdram_table[i].sz << 17);
374 /* get SDRAM bank 0 register */
375 mtdcr (memcfga, mem_mb0cf);
376 sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001;
377 sdram_bank |= (baseaddr | tmp | 0x01);
378
379 #ifdef SDRAM_DEBUG
380 serial_puts ("sdtr: ");
381 write_4hex (sdram_tim);
382 serial_puts ("\n");
383 #endif
384
385 /* write SDRAM timing register */
386 mtdcr (memcfga, mem_sdtr1);
387 mtdcr (memcfgd, sdram_tim);
388
389 #ifdef SDRAM_DEBUG
390 serial_puts ("mb0cf: ");
391 write_4hex (sdram_bank);
392 serial_puts ("\n");
393 #endif
394
395 /* write SDRAM bank 0 register */
396 mtdcr (memcfga, mem_mb0cf);
397 mtdcr (memcfgd, sdram_bank);
398
399 if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
400 /* get SDRAM refresh interval register */
401 mtdcr (memcfga, mem_rtr);
402 tmp = mfdcr (memcfgd) & ~0x3FF80000;
403 tmp |= 0x07F00000;
404 } else {
405 /* get SDRAM refresh interval register */
406 mtdcr (memcfga, mem_rtr);
407 tmp = mfdcr (memcfgd) & ~0x3FF80000;
408 tmp |= 0x05F00000;
409 }
410 /* write SDRAM refresh interval register */
411 mtdcr (memcfga, mem_rtr);
412 mtdcr (memcfgd, tmp);
413 /* enable ECC if used */
414 #if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
415 if (sdram_table[i].ecc) {
416 /* disable checking for all banks */
417 unsigned long *p;
418 #ifdef SDRAM_DEBUG
419 serial_puts ("disable ECC.. ");
420 #endif
421 mtdcr (memcfga, mem_ecccf);
422 tmp = mfdcr (memcfgd);
423 tmp &= 0xff0fffff; /* disable all banks */
424 mtdcr (memcfga, mem_ecccf);
425 /* set up SDRAM Controller with ECC enabled */
426 #ifdef SDRAM_DEBUG
427 serial_puts ("setup SDRAM Controller.. ");
428 #endif
429 mtdcr (memcfgd, tmp);
430 mtdcr (memcfga, mem_mcopt1);
431 tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000;
432 mtdcr (memcfga, mem_mcopt1);
433 mtdcr (memcfgd, tmp);
434 udelay (600);
435 #ifdef SDRAM_DEBUG
436 serial_puts ("fill the memory..\n");
437 #endif
438 serial_puts (".");
439 /* now, fill all the memory */
440 tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
441 p = (unsigned long) 0;
442 while ((unsigned long) p < tmp) {
443 *p++ = 0L;
444 if (!((unsigned long) p % 0x00800000)) /* every 8MByte */
445 serial_puts (".");
446 }
447 /* enable bank 0 */
448 serial_puts (".");
449 #ifdef SDRAM_DEBUG
450 serial_puts ("enable ECC\n");
451 #endif
452 udelay (400);
453 mtdcr (memcfga, mem_ecccf);
454 tmp = mfdcr (memcfgd);
455 tmp |= 0x00800000; /* enable bank 0 */
456 mtdcr (memcfgd, tmp);
457 udelay (400);
458 } else
459 #endif
460 {
461 /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
462 mtdcr (memcfga, mem_mcopt1);
463 tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000;
464 mtdcr (memcfga, mem_mcopt1);
465 mtdcr (memcfgd, tmp);
466 udelay (400);
467 }
468 serial_puts ("\n");
469 return (0);
470 }
471
472 int board_early_init_f (void)
473 {
474 init_sdram ();
475
476 /*-------------------------------------------------------------------------+
477 | Interrupt controller setup for the PIP405 board.
478 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
479 | IRQ 16 405GP internally generated; active low; level sensitive
480 | IRQ 17-24 RESERVED
481 | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
482 | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
483 | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
484 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
485 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
486 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
487 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
488 | Note for MIP405 board:
489 | An interrupt taken for the SouthBridge (IRQ 25) indicates that
490 | the Interrupt Controller in the South Bridge has caused the
491 | interrupt. The IC must be read to determine which device
492 | caused the interrupt.
493 |
494 +-------------------------------------------------------------------------*/
495 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
496 mtdcr (uicer, 0x00000000); /* disable all ints */
497 mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */
498 mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
499 mtdcr (uictr, 0x10000000); /* set int trigger levels */
500 mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
501 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
502 return 0;
503 }
504
505
506 /*
507 * Get some PLD Registers
508 */
509
510 unsigned short get_pld_parvers (void)
511 {
512 unsigned short result;
513 unsigned char rc;
514
515 rc = in8 (PLD_PART_REG);
516 result = (unsigned short) rc << 8;
517 rc = in8 (PLD_VERS_REG);
518 result |= rc;
519 return result;
520 }
521
522
523 void user_led0 (unsigned char on)
524 {
525 if (on)
526 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
527 else
528 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
529 }
530
531
532 void ide_set_reset (int idereset)
533 {
534 /* if reset = 1 IDE reset will be asserted */
535 if (idereset)
536 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
537 else {
538 udelay (10000);
539 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
540 }
541 }
542
543
544 /* ------------------------------------------------------------------------- */
545
546 void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
547 {
548 #if !defined(CONFIG_MIP405T)
549 unsigned char bc,rc,tmp;
550 int i;
551
552 bc = in8 (PLD_BOARD_CFG_REG);
553 tmp = ~bc;
554 tmp &= 0xf;
555 rc = 0;
556 for (i = 0; i < 4; i++) {
557 rc <<= 1;
558 rc += (tmp & 0x1);
559 tmp >>= 1;
560 }
561 rc++;
562 if(( (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */
563 || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */
564 && (rc==0x1)) /* Population Option 1 is a -3 */
565 rc=3;
566 *pcbrev=(bc >> 4) & 0xf;
567 *var=rc;
568 #else
569 unsigned char bc;
570 bc = in8 (PLD_BOARD_CFG_REG);
571 *pcbrev=(bc >> 4) & 0xf;
572 *var=16-(bc & 0xf);
573 #endif
574 }
575
576 /*
577 * Check Board Identity:
578 */
579 /* serial String: "MIP405_1000" OR "MIP405T_1000" */
580 #if !defined(CONFIG_MIP405T)
581 #define BOARD_NAME "MIP405"
582 #else
583 #define BOARD_NAME "MIP405T"
584 #endif
585
586 int checkboard (void)
587 {
588 char s[50];
589 unsigned char bc, var;
590 int i;
591 backup_t *b = (backup_t *) s;
592
593 puts ("Board: ");
594 get_pcbrev_var(&bc,&var);
595 i = getenv_r ("serial#", (char *)s, 32);
596 if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) {
597 get_backup_values (b);
598 if (strncmp (b->signature, "MPL\0", 4) != 0) {
599 puts ("### No HW ID - assuming " BOARD_NAME);
600 printf ("-%d Rev %c", var, 'A' + bc);
601 } else {
602 b->serial_name[sizeof(BOARD_NAME)-1] = 0;
603 printf ("%s-%d Rev %c SN: %s", b->serial_name, var,
604 'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]);
605 }
606 } else {
607 s[sizeof(BOARD_NAME)-1] = 0;
608 printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc,
609 &s[sizeof(BOARD_NAME)]);
610 }
611 bc = in8 (PLD_EXT_CONF_REG);
612 printf (" Boot Config: 0x%x\n", bc);
613 return (0);
614 }
615
616
617 /* ------------------------------------------------------------------------- */
618 /* ------------------------------------------------------------------------- */
619 /*
620 initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
621 the necessary info for SDRAM controller configuration
622 */
623 /* ------------------------------------------------------------------------- */
624 /* ------------------------------------------------------------------------- */
625 static int test_dram (unsigned long ramsize);
626
627 long int initdram (int board_type)
628 {
629
630 unsigned long bank_reg[4], tmp, bank_size;
631 int i, ds;
632 unsigned long TotalSize;
633
634 ds = 0;
635 /* since the DRAM controller is allready set up, calculate the size with the
636 bank registers */
637 mtdcr (memcfga, mem_mb0cf);
638 bank_reg[0] = mfdcr (memcfgd);
639 mtdcr (memcfga, mem_mb1cf);
640 bank_reg[1] = mfdcr (memcfgd);
641 mtdcr (memcfga, mem_mb2cf);
642 bank_reg[2] = mfdcr (memcfgd);
643 mtdcr (memcfga, mem_mb3cf);
644 bank_reg[3] = mfdcr (memcfgd);
645 TotalSize = 0;
646 for (i = 0; i < 4; i++) {
647 if ((bank_reg[i] & 0x1) == 0x1) {
648 tmp = (bank_reg[i] >> 17) & 0x7;
649 bank_size = 4 << tmp;
650 TotalSize += bank_size;
651 } else
652 ds = 1;
653 }
654 mtdcr (memcfga, mem_ecccf);
655 tmp = mfdcr (memcfgd);
656
657 if (!tmp)
658 printf ("No ");
659 printf ("ECC ");
660
661 test_dram (TotalSize * MEGA_BYTE);
662 return (TotalSize * MEGA_BYTE);
663 }
664
665 /* ------------------------------------------------------------------------- */
666
667
668 static int test_dram (unsigned long ramsize)
669 {
670 #ifdef SDRAM_DEBUG
671 mem_test (0L, ramsize, 1);
672 #endif
673 /* not yet implemented */
674 return (1);
675 }
676
677 /* used to check if the time in RTC is valid */
678 static unsigned long start;
679 static struct rtc_time tm;
680 extern flash_info_t flash_info[]; /* info for FLASH chips */
681
682 int misc_init_r (void)
683 {
684 DECLARE_GLOBAL_DATA_PTR;
685 /* adjust flash start and size as well as the offset */
686 gd->bd->bi_flashstart=0-flash_info[0].size;
687 gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
688 gd->bd->bi_flashoffset=0;
689
690 /* check, if RTC is running */
691 rtc_get (&tm);
692 start=get_timer(0);
693 /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
694 if (mfdcr(strap) & PSR_ROM_LOC)
695 mtspr(ccr0, (mfspr(ccr0) & ~0x80));
696
697 return (0);
698 }
699
700
701 void print_mip405_rev (void)
702 {
703 unsigned char part, vers, pcbrev, var;
704
705 get_pcbrev_var(&pcbrev,&var);
706 part = in8 (PLD_PART_REG);
707 vers = in8 (PLD_VERS_REG);
708 printf ("Rev: " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n",
709 var, pcbrev + 'A', part & 0x7F, vers);
710 }
711
712
713 #ifdef CONFIG_POST
714 /*
715 * Returns 1 if keys pressed to start the power-on long-running tests
716 * Called from board_init_f().
717 */
718 int post_hotkeys_pressed(void)
719 {
720 return 0; /* No hotkeys supported */
721 }
722 #endif
723
724 extern void mem_test_reloc(void);
725 extern int mk_date (char *, struct rtc_time *);
726
727 int last_stage_init (void)
728 {
729 unsigned long stop;
730 struct rtc_time newtm;
731 char *s;
732 mem_test_reloc();
733 /* write correct LED configuration */
734 if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
735 printf ("Error writing to the PHY\n");
736 }
737 /* since LED/CFG2 is not connected on the -2,
738 * write to correct capability information */
739 if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) {
740 printf ("Error writing to the PHY\n");
741 }
742 print_mip405_rev ();
743 show_stdio_dev ();
744 check_env ();
745 /* check if RTC time is valid */
746 stop=get_timer(start);
747 while(stop<1200) { /* we wait 1.2 sec to check if the RTC is running */
748 udelay(1000);
749 stop=get_timer(start);
750 }
751 rtc_get (&newtm);
752 if(tm.tm_sec==newtm.tm_sec) {
753 s=getenv("defaultdate");
754 if(!s)
755 mk_date ("010112001970", &newtm);
756 else
757 if(mk_date (s, &newtm)!=0) {
758 printf("RTC: Bad date format in defaultdate\n");
759 return 0;
760 }
761 rtc_reset ();
762 rtc_set(&newtm);
763 }
764 return 0;
765 }
766
767 /***************************************************************************
768 * some helping routines
769 */
770
771 int overwrite_console (void)
772 {
773 return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0); /* return TRUE if console should be overwritten */
774 }
775
776
777 /************************************************************************
778 * Print MIP405 Info
779 ************************************************************************/
780 void print_mip405_info (void)
781 {
782 unsigned char part, vers, cfg, irq_reg, com_mode, ext;
783
784 part = in8 (PLD_PART_REG);
785 vers = in8 (PLD_VERS_REG);
786 cfg = in8 (PLD_BOARD_CFG_REG);
787 irq_reg = in8 (PLD_IRQ_REG);
788 com_mode = in8 (PLD_COM_MODE_REG);
789 ext = in8 (PLD_EXT_CONF_REG);
790
791 printf ("PLD Part %d version %d\n", part & 0x7F, vers);
792 printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
793 printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
794 (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
795 printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
796 printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
797 #if !defined(CONFIG_MIP405T)
798 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
799 (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
800 (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
801 (ext >> 6) & 0x1, (ext >> 7) & 0x1);
802 printf ("SER1 uses handshakes %s\n",
803 (ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
804 #else
805 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
806 (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
807 (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
808 (ext >> 6) & 0x1,(ext >> 7) & 0x1);
809 #endif
810 printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
811 printf ("IRQs:\n");
812 printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
813 #if !defined(CONFIG_MIP405T)
814 printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
815 printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
816 #endif
817 printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active");
818 printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
819 printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active");
820 }
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