]>
git.ipfire.org Git - people/ms/u-boot.git/blob - board/mpl/pati/cmd_pati.c
3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
5 * SPDX-License-Identifier: GPL-2.0+
15 #include "pci_eeprom.h"
17 extern void show_pld_regs(void);
18 extern int do_mplcommon(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[]);
20 extern void user_led0(int led_on
);
21 extern void user_led1(int led_on
);
23 /* ------------------------------------------------------------------------- */
24 #if defined(CONFIG_SYS_PCI_CON_DEVICE)
25 extern void pci_con_disc(void);
26 extern void pci_con_connect(void);
29 /******************************************************************************
31 ******************************************************************************/
32 unsigned long get32(unsigned long addr
)
34 unsigned long *p
=(unsigned long *)addr
;
38 void set32(unsigned long addr
,unsigned long data
)
40 unsigned long *p
=(unsigned long *)addr
;
44 #define PCICFG_GET_REG(x) (get32((x) + PCI_CONFIG_BASE))
45 #define PCICFG_SET_REG(x,y) (set32((x) + PCI_CONFIG_BASE,(y)))
48 /******************************************************************************
50 ******************************************************************************/
52 static void reload_pci_eeprom(void)
55 /* Set Bit 29 and clear it again */
56 reg
=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT
);
60 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
);
61 /* EECLK @ 33MHz = 125kHz
62 * -> extra long load = 32 * 16bit = 512Bit @ 125kHz = 4.1msec
65 udelay(20000); /* wait 20ms */
66 reg
&= ~(1<<29); /* set it low */
67 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
);
68 udelay(1); /* wait some time */
71 /******************************************************************************
73 ******************************************************************************/
75 static void clock_pci_eeprom(void)
78 /* clock is low, data is valid */
79 reg
=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT
);
83 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
);
84 udelay(1); /* wait some time */
85 reg
&= ~(1<<24); /* set clock low */
86 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
);
87 udelay(1); /* wait some time */
90 /******************************************************************************
92 ******************************************************************************/
93 static void send_pci_eeprom_cmd(unsigned long cmd
, unsigned char len
)
97 reg
=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT
);
98 /* Clear all EEPROM bits */
100 /* Toggle EEPROM's Chip select to get it out of Shift Register Mode */
101 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
);
102 udelay(1); /* wait some time */
103 /* Enable EEPROM Chip Select */
105 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
);
106 /* Send EEPROM command - one bit at a time */
107 for (i
= (int)(len
-1); i
>= 0; i
--) {
108 /* Check if current bit is 0 or 1 */
110 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,(reg
| (1<<26)));
112 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
);
117 /******************************************************************************
118 * write_pci_eeprom_offs
119 ******************************************************************************/
120 static void write_pci_eeprom_offs(unsigned short offset
, unsigned short value
)
123 int bitpos
, cmdshft
, cmdlen
, timeout
;
124 /* we're using the Eeprom 93CS66 */
126 cmdlen
= EE66_CMD_LEN
;
127 /* Send Write_Enable command to EEPROM */
128 send_pci_eeprom_cmd((EE_WREN
<< cmdshft
),cmdlen
);
129 /* Send EEPROM Write command and offset to EEPROM */
130 send_pci_eeprom_cmd((EE_WRITE
<< cmdshft
) | (offset
/ 2),cmdlen
);
131 reg
=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT
);
132 /* Clear all EEPROM bits */
134 /* Make sure EEDO Input is disabled for some PLX chips */
136 /* Enable EEPROM Chip Select */
138 /* Write 16-bit value to EEPROM - one bit at a time */
139 for (bitpos
= 15; bitpos
>= 0; bitpos
--) {
140 /* Get bit value and shift into result */
141 if (value
& (1 << bitpos
))
142 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,(reg
| (1<<26)));
144 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
);
148 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
& ~(1 << 25));
150 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
| (1 << 25));
151 /* A small delay is needed to let EEPROM complete */
155 reg
=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT
);
157 } while (((reg
& (1 << 27)) == 0) && timeout
< 20000);
158 /* Send Write_Disable command to EEPROM */
159 send_pci_eeprom_cmd((EE_WDS
<< cmdshft
),cmdlen
);
160 /* Clear Chip Select and all other EEPROM bits */
161 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
& ~(0xF << 24));
165 /******************************************************************************
166 * read_pci_eeprom_offs
167 ******************************************************************************/
168 static void read_pci_eeprom_offs(unsigned short offset
, unsigned short *pvalue
)
171 int bitpos
, cmdshft
, cmdlen
;
172 /* we're using the Eeprom 93CS66 */
174 cmdlen
= EE66_CMD_LEN
;
175 /* Send EEPROM read command and offset to EEPROM */
176 send_pci_eeprom_cmd((EE_READ
<< cmdshft
) | (offset
/ 2),cmdlen
);
177 /* Set EEPROM write output bit */
178 reg
=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT
);
179 /* Set EEDO Input enable */
181 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
| (1 << 26));
182 /* Get 16-bit value from EEPROM - one bit at a time */
183 for (bitpos
= 0; bitpos
< 16; bitpos
++) {
186 reg
=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT
);
187 /* Get bit value and shift into result */
189 *pvalue
= (unsigned short)((*pvalue
<< 1) | 1);
191 *pvalue
= (unsigned short)(*pvalue
<< 1);
193 /* Clear EEDO Input enable */
195 /* Clear Chip Select and all other EEPROM bits */
196 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
& ~(0xF << 24));
200 /******************************************************************************
202 ******************************************************************************/
205 static int pati_pci_eeprom_erase(void)
208 printf("Erasing EEPROM ");
209 for( i
=0; i
< PATI_EEPROM_LAST_OFFSET
; i
+=2) {
210 write_pci_eeprom_offs(i
,0xffff);
218 static int pati_pci_eeprom_prg(void)
222 printf("Programming EEPROM ");
223 while(pati_eeprom
[i
].offset
<0xffff) {
224 write_pci_eeprom_offs(pati_eeprom
[i
].offset
,pati_eeprom
[i
].value
);
226 printf("0x%04X: 0x%04X\n",pati_eeprom
[i
].offset
, pati_eeprom
[i
].value
);
237 static int pati_pci_eeprom_write(unsigned short offset
, unsigned long addr
, unsigned short size
)
240 unsigned short value
;
241 unsigned short *buffer
=(unsigned short *)addr
;
242 if((offset
+ size
) > PATI_EEPROM_LAST_OFFSET
) {
243 size
= PATI_EEPROM_LAST_OFFSET
- offset
;
245 printf("Write To EEPROM from 0x%lX to 0x%X 0x%X words\n", addr
, offset
, size
/2);
246 for( i
= offset
; i
< (offset
+ size
); i
+=2) {
248 write_pci_eeprom_offs(i
,value
);
250 printf("0x%04X: 0x%04X\n",i
, value
);
260 static int pati_pci_eeprom_read(unsigned short offset
, unsigned long addr
, unsigned short size
)
263 unsigned short value
= 0;
264 unsigned short *buffer
=(unsigned short *)addr
;
265 if((offset
+ size
) > PATI_EEPROM_LAST_OFFSET
) {
266 size
= PATI_EEPROM_LAST_OFFSET
- offset
;
268 printf("Read from EEPROM from 0x%X to 0x%lX 0x%X words\n", offset
, addr
, size
/2);
269 for( i
= offset
; i
< (offset
+ size
); i
+=2) {
270 read_pci_eeprom_offs(i
,&value
);
273 printf("0x%04X: 0x%04X\n",i
, value
);
283 /******************************************************************************
284 * PCI Bridge Registers Dump
285 *******************************************************************************/
286 static void display_pci_regs(void)
288 printf(" PCI9056_SPACE0_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_RANGE
));
289 printf(" PCI9056_SPACE0_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_REMAP
));
290 printf(" PCI9056_LOCAL_DMA_ARBIT %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_DMA_ARBIT
));
291 printf(" PCI9056_ENDIAN_DESC %08lX\n",PCICFG_GET_REG(PCI9056_ENDIAN_DESC
));
292 printf(" PCI9056_EXP_ROM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_RANGE
));
293 printf(" PCI9056_EXP_ROM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_REMAP
));
294 printf(" PCI9056_SPACE0_ROM_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_ROM_DESC
));
295 printf(" PCI9056_DM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_DM_RANGE
));
296 printf(" PCI9056_DM_MEM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_MEM_BASE
));
297 printf(" PCI9056_DM_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_IO_BASE
));
298 printf(" PCI9056_DM_PCI_MEM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_MEM_REMAP
));
299 printf(" PCI9056_DM_PCI_IO_CONFIG %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_IO_CONFIG
));
300 printf(" PCI9056_SPACE1_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_RANGE
));
301 printf(" PCI9056_SPACE1_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_REMAP
));
302 printf(" PCI9056_SPACE1_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_DESC
));
303 printf(" PCI9056_DM_DAC %08lX\n",PCICFG_GET_REG(PCI9056_DM_DAC
));
304 printf(" PCI9056_MAILBOX0 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX0
));
305 printf(" PCI9056_MAILBOX1 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX1
));
306 printf(" PCI9056_MAILBOX2 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX2
));
307 printf(" PCI9056_MAILBOX3 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX3
));
308 printf(" PCI9056_MAILBOX4 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX4
));
309 printf(" PCI9056_MAILBOX5 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX5
));
310 printf(" PCI9056_MAILBOX6 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX6
));
311 printf(" PCI9056_MAILBOX7 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX7
));
312 printf(" PCI9056_PCI_TO_LOC_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_PCI_TO_LOC_DBELL
));
313 printf(" PCI9056_LOC_TO_PCI_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_LOC_TO_PCI_DBELL
));
314 printf(" PCI9056_INT_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_INT_CTRL_STAT
));
315 printf(" PCI9056_EEPROM_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT
));
316 printf(" PCI9056_PERM_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_PERM_VENDOR_ID
));
317 printf(" PCI9056_REVISION_ID %08lX\n",PCICFG_GET_REG(PCI9056_REVISION_ID
));
319 printf(" PCI9056_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_VENDOR_ID
));
320 printf(" PCI9056_COMMAND %08lX\n",PCICFG_GET_REG(PCI9056_COMMAND
));
321 printf(" PCI9056_REVISION %08lX\n",PCICFG_GET_REG(PCI9056_REVISION
));
322 printf(" PCI9056_CACHE_SIZE %08lX\n",PCICFG_GET_REG(PCI9056_CACHE_SIZE
));
323 printf(" PCI9056_RTR_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_BASE
));
324 printf(" PCI9056_RTR_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_IO_BASE
));
325 printf(" PCI9056_LOCAL_BASE0 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE0
));
326 printf(" PCI9056_LOCAL_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE1
));
327 printf(" PCI9056_UNUSED_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE1
));
328 printf(" PCI9056_UNUSED_BASE2 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE2
));
329 printf(" PCI9056_CIS_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CIS_PTR
));
330 printf(" PCI9056_SUB_ID %08lX\n",PCICFG_GET_REG(PCI9056_SUB_ID
));
331 printf(" PCI9056_EXP_ROM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_BASE
));
332 printf(" PCI9056_CAP_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CAP_PTR
));
333 printf(" PCI9056_INT_LINE %08lX\n",PCICFG_GET_REG(PCI9056_INT_LINE
));
334 printf(" PCI9056_PM_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_PM_CAP_ID
));
335 printf(" PCI9056_PM_CSR %08lX\n",PCICFG_GET_REG(PCI9056_PM_CSR
));
336 printf(" PCI9056_HS_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_HS_CAP_ID
));
337 printf(" PCI9056_VPD_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_VPD_CAP_ID
));
338 printf(" PCI9056_VPD_DATA %08lX\n",PCICFG_GET_REG(PCI9056_VPD_DATA
));
342 int do_pati(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
344 if (strcmp(argv
[1], "info") == 0)
349 if (strcmp(argv
[1], "pci") == 0)
354 if (strcmp(argv
[1], "led") == 0)
357 led_nr
= (int)simple_strtoul(argv
[2], NULL
, 10);
358 led_on
= (int)simple_strtoul(argv
[3], NULL
, 10);
365 #if defined(CONFIG_SYS_PCI_CON_DEVICE)
366 if (strcmp(argv
[1], "con") == 0) {
370 if (strcmp(argv
[1], "disc") == 0) {
375 if (strcmp(argv
[1], "eeprom") == 0) {
379 size
= PATI_EEPROM_LAST_OFFSET
;
382 addr
= simple_strtoul(argv
[3], NULL
, 16);
384 offset
= (int) simple_strtoul(argv
[4], NULL
, 16);
386 size
= (int) simple_strtoul(argv
[5], NULL
, 16);
387 if (strcmp(argv
[2], "read") == 0) {
388 return (pati_pci_eeprom_read(offset
, addr
, size
));
390 if (strcmp(argv
[2], "write") == 0) {
391 return (pati_pci_eeprom_write(offset
, addr
, size
));
394 if (strcmp(argv
[2], "prg") == 0) {
395 return (pati_pci_eeprom_prg());
397 if (strcmp(argv
[2], "era") == 0) {
398 return (pati_pci_eeprom_erase());
400 if (strcmp(argv
[2], "reload") == 0) {
409 return (do_mplcommon(cmdtp
, flag
, argc
, argv
));
414 "PATI specific Cmds",
415 "info - displays board information\n"
416 "pati pci - displays PCI registers\n"
417 "pati led <nr> <on> \n"
418 " - switch LED <nr> <on>\n"
419 "pati flash mem [SrcAddr]\n"
420 " - updates U-Boot with image in memory\n"
421 "pati eeprom <cmd> - PCI EEPROM sub-system\n"
422 " read <addr> <offset> <size>\n"
423 " - read PCI EEPROM to <addr> from <offset> <size> words\n"
424 " write <addr> <offset> <size>\n"
425 " - write PCI EEPROM from <addr> to <offset> <size> words\n"
426 " prg - programm PCI EEPROM with default values\n"
427 " era - erase PCI EEPROM (write all word to 0xffff)\n"
428 " reload- Reload PCI Bridge with EEPROM Values\n"
429 " NOTE: <addr> must start on word boundary\n"
430 " <offset> and <size> must be even byte values"
433 /* ------------------------------------------------------------------------- */