board/mpl/pati/pci_eeprom.h

   1 #ifndef __PCI_EEPROM_H_
   2 #define __PCI_EEPROM_H_ 1
   3
   4 #include "pati.h"
   5 /******************************************************************************
   6  * Eeprom Support
   7  ******************************************************************************/
   8 /**********************************************
   9 *               Definitions
  10 **********************************************/
  11 #define EE46_CMD_LEN    9       /* Bits in instructions */
  12 #define EE56_CMD_LEN    11      /* Bits in instructions */
  13 #define EE66_CMD_LEN    11      /* Bits in instructions */
  14 #define EE_READ         0x0180  /* 01 1000 0000 read instruction */
  15 #define EE_WRITE        0x0140  /* 01 0100 0000 write instruction */
  16 #define EE_WREN         0x0130  /* 01 0011 0000 write enable instruction */
  17 #define EE_WRALL        0x0110  /* 01 0001 0000 write all registers */
  18 #define EE_PRREAD       0x0180  /* 01 1000 0000 read address stored in Protect Register */
  19 #define EE_PRWRITE      0x0140  /* 01 0100 0000 write the address into PR */
  20 #define EE_WDS          0x0100  /* 01 0000 0000 write disable instruction */
  21 #define EE_PREN         0x0130  /* 01 0011 0000 protect enable instruction */
  22 #define EE_PRCLEAR      0x01FF  /* 01 1111 1111 clear protect register instr */
  23 #define EE_PRDS         0x0100  /* 01 0000 0000 ONE TIME ONLY, permenant */
  24
  25 /***************************************************
  26  * EEPROM
  27  ***************************************************/
  28 #define LOW_WORD(x)     (((x) & 0xFFFF))
  29 #define HIGH_WORD(x)    (((x) >> 16) & 0xFFFF)
  30
  31 typedef struct pci_eeprom_t {
  32         unsigned short offset;
  33         unsigned short value;
  34 } pci_eeprom;
  35
  36 static pci_eeprom pati_eeprom[] = {
  37         { 0x00,PCI_DEVICE_ID_PATI },    /* PCI Device ID PCIIDR[31:16] */
  38         { 0x02,PCI_VENDOR_ID_MPL },     /* PCI Vendor ID PCIIDR[15:0] */
  39         { 0x04,PCI_CLASS_PROCESSOR_POWERPC },   /* PCI Class Code PCICCR[23:8] */
  40         { 0x06,0x00BA },        /* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */
  41         { 0x08,0x0007 },        /* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */
  42         { 0x0A,0x0100 },        /* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */
  43         { 0x0C,0x0000 },        /* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */
  44         { 0x0E,0x0000 },        /* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */
  45         { 0x10,0x0000 },        /* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */
  46         { 0x12,0x0000 },        /* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */
  47         { 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) },  /* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */
  48         { 0x16,LOW_WORD(PATI_LOC_CFG_MASK) },   /* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */
  49         { 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) },  /* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */
  50         { 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 }, /* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */
  51         { 0x1C,0x0000 },        /* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */
  52         { 0x1E,0x0000 },        /* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */
  53         { 0x20,0x0030 },        /* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */
  54         { 0x22,0x0510 },        /* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */
  55         { 0x24,0x0000 },        /* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */
  56         { 0x26,0x0000 },        /* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1]  */
  57         { 0x28,0x0000 },        /* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */
  58         { 0x2A,0x0000 },        /* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */
  59         { 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) },      /* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */
  60         { 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) },    /* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */
  61         { 0x30,HIGH_WORD(PATI_DMASTER_MASK) },  /* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */
  62         { 0x32,LOW_WORD(PATI_DMASTER_MASK) },   /* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */
  63         { 0x34,HIGH_WORD(PATI_DMASTER_ADDR) },  /* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */
  64         { 0x36,LOW_WORD(PATI_DMASTER_ADDR) },   /* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */
  65         { 0x38,0x0000 },        /* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */
  66         { 0x3A,0x0000 },        /* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */
  67         { 0x3C,0x0000 },        /* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */
  68         { 0x3E,0x0000 },        /* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */
  69         { 0x40,0x0000 },        /* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/
  70         { 0x42,0x0000 },        /* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */
  71         { 0x44,0x0000 },        /* PCI Subsystem ID PCISID[15:0] */
  72         { 0x46,0x0000 },        /* PCI Subsystem Vendor ID PCISVID[15:0] */
  73         { 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) },        /* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */
  74         { 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) }, /* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */
  75         { 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) },        /* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */
  76         { 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 },   /* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */
  77         { 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */
  78         { 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) },  /* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */
  79         { 0x54,0x0000 },        /* Hot Swap Control/Status (Reserved) Reserved */
  80         { 0x56,0x0000 },        /* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */
  81         { 0x58,0x0000 },        /* Reserved Reserved */
  82         { 0x5A,0x0000 },        /* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */
  83         { 0x5C,0x0000 },        /* Power Management Capabilities PMC[15:9, 2:0] */
  84         { 0x5E,0x0000 },        /* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/
  85         { 0x60,0x0000 },        /* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */
  86         { 0x62,0x0000 },        /* Power Management Control/Status PMCSR[14:8] */
  87         { 0xFFFF,0xFFFF}        /* terminaror */
  88 };
  89 #define PATI_EEPROM_LAST_OFFSET 0x64
  90 #endif /* #ifndef __PCI_EEPROM_H_ */