board/mpl/pip405/init.S

   1 /*
   2  * SPDX-License-Identifier:     GPL-2.0 ibm-pibs
   3  */
   4 /*-----------------------------------------------------------------------------
   5  * Function:     ext_bus_cntlr_init
   6  * Description:  Initializes the External Bus Controller for the external
   7  *              peripherals. IMPORTANT: For pass1 this code must run from
   8  *              cache since you can not reliably change a peripheral banks
   9  *              timing register (pbxap) while running code from that bank.
  10  *              For ex., since we are running from ROM on bank 0, we can NOT
  11  *              execute the code that modifies bank 0 timings from ROM, so
  12  *              we run it from cache.
  13  *      Bank 0 - Flash or Multi Purpose Socket
  14  *      Bank 1 - Multi Purpose Socket or Flash
  15  *      Bank 2 - not used
  16  *      Bank 3 - not used
  17  *      Bank 4 - not used
  18  *      Bank 5 - not used
  19  *      Bank 6 - used to switch on the 12V for the Multipurpose socket
  20  *      Bank 7 - Config Register
  21  *-----------------------------------------------------------------------------*/
  22 #define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
  23
  24 #include <configs/PIP405.h>
  25 #include <ppc_asm.tmpl>
  26 #include <ppc_defs.h>
  27
  28 #include <asm/cache.h>
  29 #include <asm/mmu.h>
  30 #include <asm/ppc4xx.h>
  31 #include "pip405.h"
  32
  33   .globl ext_bus_cntlr_init
  34  ext_bus_cntlr_init:
  35   mflr   r4                      /* save link register */
  36   mfdcr  r3,CPC0_PSR                /* get strapping reg */
  37   andi.  r0, r3, PSR_ROM_LOC     /* mask out irrelevant bits */
  38   bnelr                          /* jump back if PCI boot */
  39
  40   bl      ..getAddr
  41 ..getAddr:
  42   mflr    r3                      /* get address of ..getAddr */
  43   mtlr    r4                      /* restore link register */
  44   addi    r4,0,14                 /* set ctr to 14; used to prefetch */
  45   mtctr   r4                      /* 14 cache lines to fit this function */
  46                                    /* in cache (gives us 8x14=112 instrctns) */
  47 ..ebcloop:
  48   icbt    r0,r3                   /* prefetch cache line for addr in r3 */
  49   addi    r3,r3,32                                                              /* move to next cache line */
  50   bdnz    ..ebcloop               /* continue for 14 cache lines */
  51
  52    /*-------------------------------------------------------------------
  53     * Delay to ensure all accesses to ROM are complete before changing
  54     * bank 0 timings.
  55     *------------------------------------------------------------------- */
  56         addis   r3,0,0x0
  57   ori     r3,r3,0xA000
  58   mtctr   r3
  59 ..spinlp:
  60   bdnz    ..spinlp                /* spin loop */
  61
  62         /*-----------------------------------------------------------------------
  63          * decide boot up mode
  64          *----------------------------------------------------------------------- */
  65         addi            r4,0,PB0CR
  66         mtdcr           EBC0_CFGADDR,r4
  67         mfdcr           r4,EBC0_CFGDATA
  68
  69         andi.           r0, r4, 0x2000                  /* mask out irrelevant bits */
  70         beq             0f                              /* jump if 8 bit bus width */
  71
  72         /* setup 16 bit things
  73    *-----------------------------------------------------------------------
  74    * Memory Bank 0 (16 Bit Flash) initialization
  75    *---------------------------------------------------------------------- */
  76
  77         addi    r4,0,PB1AP
  78         mtdcr   EBC0_CFGADDR,r4
  79         addis   r4,0,(FLASH_AP_B)@h
  80         ori     r4,r4,(FLASH_AP_B)@l
  81         mtdcr   EBC0_CFGDATA,r4
  82
  83         addi    r4,0,PB0CR
  84         mtdcr   EBC0_CFGADDR,r4
  85         /* BS=0x010(4MB),BU=0x3(R/W), */
  86         addis   r4,0,(FLASH_CR_B)@h
  87         ori     r4,r4,(FLASH_CR_B)@l
  88         mtdcr   EBC0_CFGDATA,r4
  89         b                               1f
  90
  91 0:
  92         /* 8Bit boot mode: */
  93         /*-----------------------------------------------------------------------
  94         * Memory Bank 0 Multi Purpose Socket initialization
  95         *----------------------------------------------------------------------- */
  96         /* 0x7F8FFE80 slowest boot */
  97         addi    r4,0,PB1AP
  98         mtdcr   EBC0_CFGADDR,r4
  99         addis   r4,0,(MPS_AP_B)@h
 100         ori     r4,r4,(MPS_AP_B)@l
 101         mtdcr   EBC0_CFGDATA,r4
 102
 103         addi    r4,0,PB0CR
 104         mtdcr   EBC0_CFGADDR,r4
 105         /* BS=0x010(4MB),BU=0x3(R/W), */
 106         addis   r4,0,(MPS_CR_B)@h
 107         ori     r4,r4,(MPS_CR_B)@l
 108         mtdcr   EBC0_CFGDATA,r4
 109
 110
 111 1:
 112   /*-----------------------------------------------------------------------
 113    * Memory Bank 2-3-4-5-6 (not used) initialization
 114    *-----------------------------------------------------------------------*/
 115   addi    r4,0,PB1CR
 116   mtdcr   EBC0_CFGADDR,r4
 117   addis   r4,0,0x0000
 118   ori     r4,r4,0x0000
 119   mtdcr   EBC0_CFGDATA,r4
 120
 121   addi    r4,0,PB2CR
 122   mtdcr   EBC0_CFGADDR,r4
 123   addis   r4,0,0x0000
 124   ori     r4,r4,0x0000
 125   mtdcr   EBC0_CFGDATA,r4
 126
 127   addi    r4,0,PB3CR
 128   mtdcr   EBC0_CFGADDR,r4
 129   addis   r4,0,0x0000
 130   ori     r4,r4,0x0000
 131   mtdcr   EBC0_CFGDATA,r4
 132
 133   addi    r4,0,PB4CR
 134   mtdcr   EBC0_CFGADDR,r4
 135   addis   r4,0,0x0000
 136   ori     r4,r4,0x0000
 137   mtdcr   EBC0_CFGDATA,r4
 138
 139   addi    r4,0,PB5CR
 140   mtdcr   EBC0_CFGADDR,r4
 141   addis   r4,0,0x0000
 142   ori     r4,r4,0x0000
 143   mtdcr   EBC0_CFGDATA,r4
 144
 145   addi    r4,0,PB6CR
 146   mtdcr   EBC0_CFGADDR,r4
 147   addis   r4,0,0x0000
 148   ori     r4,r4,0x0000
 149   mtdcr   EBC0_CFGDATA,r4
 150
 151   addi    r4,0,PB7CR
 152   mtdcr   EBC0_CFGADDR,r4
 153   addis   r4,0,0x0000
 154   ori     r4,r4,0x0000
 155   mtdcr   EBC0_CFGDATA,r4
 156   nop                           /* pass2 DCR errata #8 */
 157   blr
 158
 159 #if defined(CONFIG_BOOT_PCI)
 160     .section .bootpg,"ax"
 161     .globl _start_pci
 162 /*******************************************
 163  */
 164
 165 _start_pci:
 166   /* first handle errata #68 / PCI_18 */
 167   iccci   r0, r0          /* invalidate I-cache */
 168   lis     r31, 0
 169   mticcr  r31             /* ICCR = 0 (all uncachable) */
 170   isync
 171
 172   mfccr0  r28             /* set CCR0[24] = 1 */
 173   ori     r28, r28, 0x0080
 174   mtccr0  r28
 175
 176   /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
 177   lis     r28, 0xEF40
 178   addi    r28, r28, 0x0004
 179   stw     r31, 0x0C(r28)  /* clear PMM0PCIHA */
 180   lis     r29, 0xFFF8     /* open 512 kByte */
 181   addi    r29, r29, 0x0001/* and enable this region */
 182   stwbrx  r29, r0, r28    /* write PMM0MA */
 183
 184   lis     r28, 0xEEC0     /* address of PCIC0_CFGADDR */
 185   addi    r29, r28, 4     /* add 4 to r29 -> PCIC0_CFGDATA */
 186
 187   lis     r31, 0x8000     /* set en bit bus 0 */
 188   ori     r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
 189   stwbrx  r31, r0, r28    /* write it */
 190
 191   lwbrx   r31, r0, r29    /* load XBCS register */
 192   oris    r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
 193   stwbrx  r31, r0, r29    /* write back XBCS register */
 194
 195   nop
 196   nop
 197   b     _start          /* normal start */
 198 #endif