board/mpl/vcma9/lowlevel_init.S

   1 /*
   2  * Memory Setup stuff - taken from blob memsetup.S
   3  *
   4  * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
   5  *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
   6  *
   7  * Modified for MPL VCMA9 by
   8  * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
   9  * (C) Copyright 2002, 2003, 2004, 2005
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14
  15 #include <config.h>
  16 #include <version.h>
  17
  18
  19 /* register definitions */
  20
  21 #define PLD_BASE        0x28000000
  22 #define MISC_REG        0x103
  23 #define SDRAM_REG       0x106
  24 #define BWSCON          0x48000000
  25 #define CLKBASE         0x4C000000
  26 #define LOCKTIME        0x0
  27 #define MPLLCON         0x4
  28 #define UPLLCON         0x8
  29 #define GPIOBASE        0x56000000
  30 #define GSTATUS1        0xB0
  31 #define FASTCPU         0x02
  32
  33 /* some parameters for the board */
  34 /* BWSCON */
  35 #define DW8                     (0x0)
  36 #define DW16                    (0x1)
  37 #define DW32                    (0x2)
  38 #define WAIT                    (0x1<<2)
  39 #define UBLB                    (0x1<<3)
  40
  41 /* BANKSIZE */
  42 #define BURST_EN                (0x1<<7)
  43
  44 /* BANK0CON 200 */
  45 #define B0_Tacs_200             0x0     /*  0clk  (or 0x1 1clk) */
  46 #define B0_Tcos_200             0x1     /*  1clk  (or 0x2 2clk) */
  47 #define B0_Tacc_200             0x5     /*  8clk  (or 0x6 10clk) */
  48 #define B0_Tcoh_200             0x0     /*  0clk */
  49 #define B0_Tcah_200             0x3     /*  4clk  (or0x01 1clk) */
  50 #define B0_Tacp_200             0x0     /* page mode is not used */
  51 #define B0_PMC_200              0x0     /* page mode disabled */
  52
  53 /* BANK0CON 250 */
  54 #define B0_Tacs_250             0x0     /*  0clk  (or 0x1 1clk) */
  55 #define B0_Tcos_250             0x1     /*  1clk  (or 0x2 2clk) */
  56 #define B0_Tacc_250             0x5     /*  8clk  (or 0x7 14clk) */
  57 #define B0_Tcoh_250             0x0     /*  0clk */
  58 #define B0_Tcah_250             0x3     /*  4clk  (or 0x1 1clk) */
  59 #define B0_Tacp_250             0x0     /* page mode is not used */
  60 #define B0_PMC_250              0x0     /* page mode disabled */
  61
  62 /* BANK0CON 266 */
  63 #define B0_Tacs_266             0x0     /*  0clk  (or 0x1 1clk) */
  64 #define B0_Tcos_266             0x1     /*  1clk  (or 0x2 2clk) */
  65 #define B0_Tacc_266             0x6     /*  10clk (or 0x7 14clk) */
  66 #define B0_Tcoh_266             0x0     /*  0clk */
  67 #define B0_Tcah_266             0x3     /*  4clk  (or 0x1 1clk) */
  68 #define B0_Tacp_266             0x0     /* page mode is not used */
  69 #define B0_PMC_266              0x0     /* page mode disabled */
  70
  71 /* BANK1CON 200 */
  72 #define B1_Tacs_200             0x0     /*  0clk  (or 0x1 1clk) */
  73 #define B1_Tcos_200             0x1     /*  1clk  (or 0x2 2clk) */
  74 #define B1_Tacc_200             0x5     /*  8clk  (or 0x6 10clk) */
  75 #define B1_Tcoh_200             0x0     /*  0clk */
  76 #define B1_Tcah_200             0x3     /*  4clk  (or 0x1 1clk) */
  77 #define B1_Tacp_200             0x0     /* page mode is not used */
  78 #define B1_PMC_200              0x0     /* page mode disabled */
  79
  80 /* BANK1CON 250 */
  81 #define B1_Tacs_250             0x0     /*  0clk  (or 0x1 1clk) */
  82 #define B1_Tcos_250             0x1     /*  1clk  (or 0x2 2clk) */
  83 #define B1_Tacc_250             0x5     /*  8clk  (or 0x7 14clk) */
  84 #define B1_Tcoh_250             0x0     /*  0clk */
  85 #define B1_Tcah_250             0x3     /*  4clk  (or 0x1 1clk) */
  86 #define B1_Tacp_250             0x0     /* page mode is not used */
  87 #define B1_PMC_250              0x0     /* page mode disabled */
  88
  89 /* BANK1CON 266 */
  90 #define B1_Tacs_266             0x0     /*  0clk  (or 0x1 1clk) */
  91 #define B1_Tcos_266             0x1     /*  1clk  (or 0x2 2clk) */
  92 #define B1_Tacc_266             0x6     /*  10clk (or 0x7 14clk) */
  93 #define B1_Tcoh_266             0x0     /*  0clk */
  94 #define B1_Tcah_266             0x3     /*  4clk  (or 0x1 1clk) */
  95 #define B1_Tacp_266             0x0     /* page mode is not used */
  96 #define B1_PMC_266              0x0     /* page mode disabled */
  97
  98 /* BANK2CON 200 + 250 + 266 */
  99 #define B2_Tacs                 0x3     /*  4clk */
 100 #define B2_Tcos                 0x3     /*  4clk */
 101 #define B2_Tacc                 0x7     /* 14clk */
 102 #define B2_Tcoh                 0x3     /*  4clk */
 103 #define B2_Tcah                 0x3     /*  4clk */
 104 #define B2_Tacp                 0x0     /* page mode is not used */
 105 #define B2_PMC                  0x0     /* page mode disabled */
 106
 107 /* BANK3CON 200 + 250 + 266 */
 108 #define B3_Tacs                 0x3     /*  4clk */
 109 #define B3_Tcos                 0x3     /*  4clk */
 110 #define B3_Tacc                 0x7     /* 14clk */
 111 #define B3_Tcoh                 0x3     /*  4clk */
 112 #define B3_Tcah                 0x3     /*  4clk */
 113 #define B3_Tacp                 0x0     /* page mode is not used */
 114 #define B3_PMC                  0x0     /* page mode disabled */
 115
 116 /* BANK4CON 200 */
 117 #define B4_Tacs_200             0x1     /*  1clk */
 118 #define B4_Tcos_200             0x3     /*  4clk */
 119 #define B4_Tacc_200             0x7     /* 14clk */
 120 #define B4_Tcoh_200             0x3     /*  4clk */
 121 #define B4_Tcah_200             0x2     /*  2clk */
 122 #define B4_Tacp_200             0x0     /* page mode is not used */
 123 #define B4_PMC_200              0x0     /* page mode disabled */
 124
 125 /* BANK4CON 250 */
 126 #define B4_Tacs_250             0x1     /*  1clk */
 127 #define B4_Tcos_250             0x3     /*  4clk */
 128 #define B4_Tacc_250             0x7     /* 14clk */
 129 #define B4_Tcoh_250             0x3     /*  4clk */
 130 #define B4_Tcah_250             0x2     /*  2clk */
 131 #define B4_Tacp_250             0x0     /* page mode is not used */
 132 #define B4_PMC_250              0x0     /* page mode disabled */
 133
 134 /* BANK4CON 266 */
 135 #define B4_Tacs_266             0x1     /*  1clk */
 136 #define B4_Tcos_266             0x3     /*  4clk */
 137 #define B4_Tacc_266             0x7     /* 14clk */
 138 #define B4_Tcoh_266             0x3     /*  4clk */
 139 #define B4_Tcah_266             0x2     /*  2clk */
 140 #define B4_Tacp_266             0x0     /* page mode is not used */
 141 #define B4_PMC_266              0x0     /* page mode disabled */
 142
 143 /* BANK5CON 200 */
 144 #define B5_Tacs_200             0x0     /*  0clk */
 145 #define B5_Tcos_200             0x3     /*  4clk */
 146 #define B5_Tacc_200             0x4     /*  6clk */
 147 #define B5_Tcoh_200             0x3     /*  4clk */
 148 #define B5_Tcah_200             0x1     /*  1clk */
 149 #define B5_Tacp_200             0x0     /* page mode is not used */
 150 #define B5_PMC_200              0x0     /* page mode disabled */
 151
 152 /* BANK5CON 250 */
 153 #define B5_Tacs_250             0x0     /*  0clk */
 154 #define B5_Tcos_250             0x3     /*  4clk */
 155 #define B5_Tacc_250             0x5     /*  8clk */
 156 #define B5_Tcoh_250             0x3     /*  4clk */
 157 #define B5_Tcah_250             0x1     /*  1clk */
 158 #define B5_Tacp_250             0x0     /* page mode is not used */
 159 #define B5_PMC_250              0x0     /* page mode disabled */
 160
 161 /* BANK5CON 266 */
 162 #define B5_Tacs_266             0x0     /*  0clk */
 163 #define B5_Tcos_266             0x3     /*  4clk */
 164 #define B5_Tacc_266             0x5     /*  8clk */
 165 #define B5_Tcoh_266             0x3     /*  4clk */
 166 #define B5_Tcah_266             0x1     /*  1clk */
 167 #define B5_Tacp_266             0x0     /* page mode is not used */
 168 #define B5_PMC_266              0x0     /* page mode disabled */
 169
 170 #define B6_MT                   0x3     /* SDRAM */
 171 #define B6_Trcd_200             0x0     /* 2clk */
 172 #define B6_Trcd_250             0x1     /* 3clk */
 173 #define B6_Trcd_266             0x1     /* 3clk */
 174 #define B6_SCAN                 0x2     /* 10bit */
 175
 176 #define B7_MT                   0x3     /* SDRAM */
 177 #define B7_Trcd_200             0x0     /* 2clk */
 178 #define B7_Trcd_250             0x1     /* 3clk */
 179 #define B7_Trcd_266             0x1     /* 3clk */
 180 #define B7_SCAN                 0x2     /* 10bit */
 181
 182 /* REFRESH parameter */
 183 #define REFEN                   0x1     /* Refresh enable */
 184 #define TREFMD                  0x0     /* CBR(CAS before RAS)/Auto refresh */
 185 #define Trp_200                 0x0     /* 2clk */
 186 #define Trp_250                 0x1     /* 3clk */
 187 #define Trp_266                 0x1     /* 3clk */
 188 #define Tsrc_200                0x1     /* 5clk */
 189 #define Tsrc_250                0x2     /* 6clk */
 190 #define Tsrc_266                0x3     /* 7clk */
 191
 192 /* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */
 193 #define REFCNT_200              489
 194 /* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */
 195 #define REFCNT_250              99
 196 /* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */
 197 #define REFCNT_266              0
 198 /**************************************/
 199
 200 .globl lowlevel_init
 201 lowlevel_init:
 202         /* use r0 to relocate DATA read/write to flash rather than memory ! */
 203         ldr     r0, =CONFIG_SYS_TEXT_BASE
 204         ldr     r13, =BWSCON
 205
 206         /* enable minimal access to PLD */
 207         ldr     r1, [r13]                       /* load default BWSCON */
 208         orr     r1, r1, #(DW8 + UBLB) << 20     /* set necessary CS attrs */
 209         str     r1, [r13]                       /* set BWSCON */
 210         ldr     r1, =0x7FF0                     /* select slowest timing */
 211         str     r1, [r13, #0x18]                /* set BANKCON5 */
 212
 213         ldr     r1, =PLD_BASE
 214         ldr     r2, =SETUPDATA
 215         ldrb    r1, [r1, #MISC_REG]
 216         sub     r2, r2, r0
 217         tst     r1, #FASTCPU                    /* FASTCPU available ? */
 218         addeq   r2, r2, #SETUPENTRY_SIZE
 219
 220         /* memory control configuration */
 221         /* r2 = pointer into timing table */
 222         /* r13 = pointer to MEM controller regs (starting with BWSCON) */
 223         add     r3, r2, #CSDATA_OFFSET
 224         add     r4, r3, #CSDATAENTRY_SIZE
 225 0:
 226         ldr     r1, [r3], #4
 227         str     r1, [r13], #4
 228         cmp     r3, r4
 229         bne     0b
 230
 231         /* PLD access is now possible */
 232         /* r3 = SDRAMDATA
 233         /* r13 = pointer to MEM controller regs */
 234         ldr     r1, =PLD_BASE
 235         mov     r4, #SDRAMENTRY_SIZE
 236         ldrb    r1, [r1, #SDRAM_REG]
 237         /* calculate start and end point */
 238         mla     r3, r4, r1, r3
 239         add     r4, r3, r4
 240 0:
 241         ldr     r1, [r3], #4
 242         str     r1, [r13], #4
 243         cmp     r3, r4
 244         bne     0b
 245
 246         /* setup MPLL registers */
 247         ldr     r1, =CLKBASE
 248         ldr     r4, =0xFFFFFF
 249         add     r3, r2, #4              /* r3 points to PLL values */
 250         str     r4, [r1, #LOCKTIME]
 251         ldmia   r3, {r4,r5}
 252         str     r5, [r1, #UPLLCON]      /* writing PLL register */
 253                                         /* !! order seems to be important !! */
 254         /* a little delay */
 255         ldr     r3, =0x4000
 256 0:
 257         subs    r3, r3, #1
 258         bne     0b
 259
 260         str     r4, [r1, #MPLLCON]      /* writing PLL register */
 261                                         /* !! order seems to be important !! */
 262         /* a little delay */
 263         ldr     r3, =0x4000
 264 0:
 265         subs    r3, r3, #1
 266         bne     0b
 267
 268         /* everything is fine now */
 269         mov     pc, lr
 270
 271         .ltorg
 272 /* the literal pools origin */
 273
 274 #define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \
 275         ((bws1) << 4) + \
 276         ((bws2) << 8) + \
 277         ((bws3) << 12) + \
 278         ((bws4) << 16) + \
 279         ((bws5) << 20) + \
 280         ((bws6) << 24) + \
 281         ((bws7) << 28)
 282
 283 #define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \
 284         ((tacs) << 13) + \
 285         ((tcos) << 11) + \
 286         ((tacc) << 8) + \
 287         ((tcoh) << 6) + \
 288         ((tcah) << 4) + \
 289         ((tacp) << 2) + \
 290         (pmc)
 291
 292 #define MK_BANKCON_SDRAM(trcd, scan) \
 293         ((0x03) << 15) + \
 294         ((trcd) << 2) + \
 295         (scan)
 296
 297 #define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \
 298         ((enable) << 23) + \
 299         ((trefmd) << 22) + \
 300         ((trp) << 20) + \
 301         ((tsrc) << 18) + \
 302         (cnt)
 303
 304 SETUPDATA:
 305         .word 0x32410002
 306         /* PLL values (MDIV, PDIV, SDIV) for 250 MHz */
 307         .word (0x75 << 12) + (0x01 << 4) + (0x01 << 0)
 308         /* PLL values for USB clock */
 309         .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
 310
 311         /* timing for 250 MHz*/
 312 0:
 313         .equiv CSDATA_OFFSET, (. - SETUPDATA)
 314         .word MK_BWSCON(DW16, \
 315                         DW32, \
 316                         DW32, \
 317                         DW16 + WAIT + UBLB, \
 318                         DW8 + UBLB, \
 319                         DW32, \
 320                         DW32)
 321
 322         .word MK_BANKCON(B0_Tacs_250, \
 323                          B0_Tcos_250, \
 324                          B0_Tacc_250, \
 325                          B0_Tcoh_250, \
 326                          B0_Tcah_250, \
 327                          B0_Tacp_250, \
 328                          B0_PMC_250)
 329
 330         .word MK_BANKCON(B1_Tacs_250, \
 331                          B1_Tcos_250, \
 332                          B1_Tacc_250, \
 333                          B1_Tcoh_250, \
 334                          B1_Tcah_250, \
 335                          B1_Tacp_250, \
 336                          B1_PMC_250)
 337
 338         .word MK_BANKCON(B2_Tacs, \
 339                          B2_Tcos, \
 340                          B2_Tacc, \
 341                          B2_Tcoh, \
 342                          B2_Tcah, \
 343                          B2_Tacp, \
 344                          B2_PMC)
 345
 346         .word MK_BANKCON(B3_Tacs, \
 347                          B3_Tcos, \
 348                          B3_Tacc, \
 349                          B3_Tcoh, \
 350                          B3_Tcah, \
 351                          B3_Tacp, \
 352                          B3_PMC)
 353
 354         .word MK_BANKCON(B4_Tacs_250, \
 355                          B4_Tcos_250, \
 356                          B4_Tacc_250, \
 357                          B4_Tcoh_250, \
 358                          B4_Tcah_250, \
 359                          B4_Tacp_250, \
 360                          B4_PMC_250)
 361
 362         .word MK_BANKCON(B5_Tacs_250, \
 363                          B5_Tcos_250, \
 364                          B5_Tacc_250, \
 365                          B5_Tcoh_250, \
 366                          B5_Tcah_250, \
 367                          B5_Tacp_250, \
 368                          B5_PMC_250)
 369
 370         .equiv CSDATAENTRY_SIZE, (. - 0b)
 371         /* 4Mx8x4 */
 372 0:
 373         .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
 374         .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
 375         .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
 376         .word 0x32 + BURST_EN
 377         .word 0x30
 378         .word 0x30
 379         .equiv SDRAMENTRY_SIZE, (. - 0b)
 380
 381         /* 8Mx8x4 */
 382         .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
 383         .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
 384         .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
 385         .word 0x32 + BURST_EN
 386         .word 0x30
 387         .word 0x30
 388
 389         /* 2Mx8x4 */
 390         .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
 391         .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
 392         .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
 393         .word 0x32 + BURST_EN
 394         .word 0x30
 395         .word 0x30
 396
 397         /* 4Mx8x2 */
 398         .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
 399         .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
 400         .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
 401         .word 0x32 + BURST_EN
 402         .word 0x30
 403         .word 0x30
 404
 405         .equiv SETUPENTRY_SIZE, (. - SETUPDATA)
 406
 407         .word 0x32410000
 408         /* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */
 409         .word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0)
 410         /* PLL values for USB clock */
 411         .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
 412
 413         /* timing for 200 MHz and default*/
 414         .word MK_BWSCON(DW16, \
 415                         DW32, \
 416                         DW32, \
 417                         DW16 + WAIT + UBLB, \
 418                         DW8 + UBLB, \
 419                         DW32, \
 420                         DW32)
 421
 422         .word MK_BANKCON(B0_Tacs_200, \
 423                          B0_Tcos_200, \
 424                          B0_Tacc_200, \
 425                          B0_Tcoh_200, \
 426                          B0_Tcah_200, \
 427                          B0_Tacp_200, \
 428                          B0_PMC_200)
 429
 430         .word MK_BANKCON(B1_Tacs_200, \
 431                          B1_Tcos_200, \
 432                          B1_Tacc_200, \
 433                          B1_Tcoh_200, \
 434                          B1_Tcah_200, \
 435                          B1_Tacp_200, \
 436                          B1_PMC_200)
 437
 438         .word MK_BANKCON(B2_Tacs, \
 439                          B2_Tcos, \
 440                          B2_Tacc, \
 441                          B2_Tcoh, \
 442                          B2_Tcah, \
 443                          B2_Tacp, \
 444                          B2_PMC)
 445
 446         .word MK_BANKCON(B3_Tacs, \
 447                          B3_Tcos, \
 448                          B3_Tacc, \
 449                          B3_Tcoh, \
 450                          B3_Tcah, \
 451                          B3_Tacp, \
 452                          B3_PMC)
 453
 454         .word MK_BANKCON(B4_Tacs_200, \
 455                          B4_Tcos_200, \
 456                          B4_Tacc_200, \
 457                          B4_Tcoh_200, \
 458                          B4_Tcah_200, \
 459                          B4_Tacp_200, \
 460                          B4_PMC_200)
 461
 462         .word MK_BANKCON(B5_Tacs_200, \
 463                          B5_Tcos_200, \
 464                          B5_Tacc_200, \
 465                          B5_Tcoh_200, \
 466                          B5_Tcah_200, \
 467                          B5_Tacp_200, \
 468                          B5_PMC_200)
 469
 470         /* 4Mx8x4 */
 471         .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
 472         .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
 473         .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
 474         .word 0x32 + BURST_EN
 475         .word 0x30
 476         .word 0x30
 477
 478         /* 8Mx8x4 */
 479         .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
 480         .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
 481         .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
 482         .word 0x32 + BURST_EN
 483         .word 0x30
 484         .word 0x30
 485
 486         /* 2Mx8x4 */
 487         .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
 488         .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
 489         .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
 490         .word 0x32 + BURST_EN
 491         .word 0x30
 492         .word 0x30
 493
 494         /* 4Mx8x2 */
 495         .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
 496         .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
 497         .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
 498         .word 0x32 + BURST_EN
 499         .word 0x30
 500         .word 0x30
 501
 502         .equiv SETUPDATA_SIZE, (. - SETUPDATA)