board/mpl/vcma9/memsetup.S

   1 /*
   2  * Memory Setup stuff - taken from blob memsetup.S
   3  *
   4  * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
   5  *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
   6  *
   7  * Modified for the Samsung SMDK2410 by
   8  * (C) Copyright 2002
   9  * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30
  31 #include <config.h>
  32 #include <version.h>
  33
  34
  35 /* some parameters for the board */
  36
  37 #define BWSCON  0x48000000
  38
  39 /* BWSCON */
  40 #define DW8                     (0x0)
  41 #define DW16                    (0x1)
  42 #define DW32                    (0x2)
  43 #define WAIT                    (0x1<<2)
  44 #define UBLB                    (0x1<<3)
  45
  46 #define B1_BWSCON               (DW16)
  47 #define B2_BWSCON               (DW32)
  48 #define B3_BWSCON               (DW32)
  49 #define B4_BWSCON               (DW16 + WAIT + UBLB)
  50 #define B5_BWSCON               (DW8 + UBLB)
  51 #define B6_BWSCON               (DW32)
  52 #define B7_BWSCON               (DW32)
  53
  54 /* BANK0CON */
  55 #define B0_Tacs                 0x0     /*  0clk */
  56 #define B0_Tcos                 0x1     /*  1clk */
  57 /*#define B0_Tcos               0x0       0clk */
  58 #define B0_Tacc                 0x7     /*  14clk */
  59 /*#define B0_Tacc               0x5       8clk */
  60 #define B0_Tcoh                 0x0     /*  0clk */
  61 #define B0_Tah                  0x0     /*  0clk */
  62 #define B0_Tacp                 0x0     /* page mode is not used */
  63 #define B0_PMC                  0x0     /* page mode disabled */
  64
  65 /* BANK1CON */
  66 #define B1_Tacs                 0x0     /*  0clk */
  67 #define B1_Tcos                 0x1     /*  1clk */
  68 /*#define B1_Tcos               0x0       0clk */
  69 #define B1_Tacc                 0x7     /*  14clk */
  70 /*#define B1_Tacc               0x5       8clk */
  71 #define B1_Tcoh                 0x0     /*  0clk */
  72 #define B1_Tah                  0x0     /*  0clk */
  73 #define B1_Tacp                 0x0     /* page mode is not used */
  74 #define B1_PMC                  0x0     /* page mode disabled */
  75
  76 #define B2_Tacs                 0x3     /*  4clk */
  77 #define B2_Tcos                 0x3     /*  4clk */
  78 #define B2_Tacc                 0x7     /* 14clk */
  79 #define B2_Tcoh                 0x3     /*  4clk */
  80 #define B2_Tah                  0x3     /*  4clk */
  81 #define B2_Tacp                 0x0     /* page mode is not used */
  82 #define B2_PMC                  0x0     /* page mode disabled */
  83
  84 #define B3_Tacs                 0x3     /*  4clk */
  85 #define B3_Tcos                 0x3     /*  4clk */
  86 #define B3_Tacc                 0x7     /* 14clk */
  87 #define B3_Tcoh                 0x3     /*  4clk */
  88 #define B3_Tah                  0x3     /*  4clk */
  89 #define B3_Tacp                 0x0     /* page mode is not used */
  90 #define B3_PMC                  0x0     /* page mode disabled */
  91
  92 #define B4_Tacs                 0x3     /*  4clk */
  93 #define B4_Tcos                 0x1     /*  1clk */
  94 #define B4_Tacc                 0x7     /* 14clk */
  95 #define B4_Tcoh                 0x1     /*  1clk */
  96 #define B4_Tah                  0x0     /*  0clk */
  97 #define B4_Tacp                 0x0     /* page mode is not used */
  98 #define B4_PMC                  0x0     /* page mode disabled */
  99
 100 #define B5_Tacs                 0x0     /*  0clk */
 101 #define B5_Tcos                 0x3     /*  4clk */
 102 #define B5_Tacc                 0x5     /*  8clk */
 103 #define B5_Tcoh                 0x2     /*  2clk */
 104 #define B5_Tah                  0x1     /*  1clk */
 105 #define B5_Tacp                 0x0     /* page mode is not used */
 106 #define B5_PMC                  0x0     /* page mode disabled */
 107
 108 #define B6_MT                   0x3     /* SDRAM */
 109 #define B6_Trcd                 0x1     /* 3clk */
 110 #define B6_SCAN                 0x2     /* 10bit */
 111
 112 #define B7_MT                   0x3     /* SDRAM */
 113 #define B7_Trcd                 0x1     /* 3clk */
 114 #define B7_SCAN                 0x2     /* 10bit */
 115
 116 /* REFRESH parameter */
 117 #define REFEN                   0x1     /* Refresh enable */
 118 #define TREFMD                  0x0     /* CBR(CAS before RAS)/Auto refresh */
 119 #define Trp                     0x0     /* 2clk */
 120 #define Trc                     0x3     /* 7clk */
 121 #define Tchr                    0x2     /* 3clk */
 122 #define REFCNT                  1113    /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
 123 /**************************************/
 124
 125 _TEXT_BASE:
 126         .word   TEXT_BASE
 127
 128 .globl memsetup
 129 memsetup:
 130         /* memory control configuration */
 131         /* make r0 relative the current location so that it */
 132         /* reads SMRDATA out of FLASH rather than memory ! */
 133         ldr     r0, =SMRDATA
 134         ldr     r1, _TEXT_BASE
 135         sub     r0, r0, r1
 136         ldr     r1, =BWSCON     /* Bus Width Status Controller */
 137         add     r2, r0, #13*4
 138 0:
 139         ldr     r3, [r0], #4
 140         str     r3, [r1], #4
 141         cmp     r2, r0
 142         bne     0b
 143
 144         /* everything is fine now */
 145         mov     pc, lr
 146
 147         .ltorg
 148 /* the literal pools origin */
 149
 150 SMRDATA:
 151     .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
 152     .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
 153     .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
 154     .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
 155     .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
 156     .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
 157     .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
 158     .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
 159     .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
 160     .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
 161     .word 0x32
 162     .word 0x30
 163     .word 0x30