board/mpr2/lowlevel_init.S

   1 /*
   2  * (C) Copyright 2008
   3  * Mark Jonas <mark.jonas@de.bosch.com>
   4  *
   5  * (C) Copyright 2007
   6  * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
   7  *
   8  * board/mpr2/lowlevel_init.S
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12 #include <asm/macro.h>
  13
  14         .global lowlevel_init
  15
  16         .text
  17         .align  2
  18
  19 lowlevel_init:
  20
  21 /*
  22  * Set frequency multipliers and dividers in FRQCR.
  23  */
  24         write16 WTCSR_A, WTCSR_D
  25
  26         write16 WTCNT_A, WTCNT_D
  27
  28         write16 FRQCR_A, FRQCR_D
  29
  30 /*
  31  * Setup CS0 (Flash).
  32  */
  33         write32 CS0BCR_A, CS0BCR_D
  34
  35         write32 CS0WCR_A, CS0WCR_D
  36
  37 /*
  38  * Setup CS3 (SDRAM).
  39  */
  40         write32 CS3BCR_A, CS3BCR_D
  41
  42         write32 CS3WCR_A, CS3WCR_D
  43
  44         write32 SDCR_A, SDCR_D1
  45
  46         write32 RTCSR_A, RTCSR_D
  47
  48         write32 RTCNT_A, RTCNT_D
  49
  50         write32 RTCOR_A, RTCOR_D
  51
  52         write32 SDCR_A, SDCR_D2
  53
  54         mov.l   SDMR3_A, r1
  55         mov.l   SDMR3_D, r0
  56         add     r0, r1
  57         mov     #0, r0
  58         mov.w   r0, @r1
  59
  60         rts
  61         nop
  62
  63         .align 4
  64
  65 /*
  66  * Configuration for MPR2 A.3 through A.7
  67  */
  68
  69 /*
  70  * PLL Settings
  71  */
  72 FRQCR_D:        .word   0x1103          /* I:B:P=8:4:2 */
  73 WTCNT_D:        .word   0x5A00          /* start counting at zero */
  74 WTCSR_D:        .word   0xA507          /* divide by 4096 */
  75 .align 2
  76 /*
  77  * Spansion S29GL256N11 @ 48 MHz
  78  */
  79 /* 1 idle cycle inserted, normal space, 16 bit */
  80 CS0BCR_D:       .long   0x12490400
  81 /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
  82 CS0WCR_D:       .long   0x00000340
  83
  84 /*
  85  * Samsung K4S511632B-UL75 @ 48 MHz
  86  * Micron MT48LC32M16A2-75 @ 48 MHz
  87  */
  88 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
  89 CS3BCR_D:       .long   0x10004400
  90 /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
  91 CS3WCR_D:       .long   0x00000091
  92 /* no refresh, 13 rows, 10 cols, NO bank active mode */
  93 SDCR_D1:        .long   0x00000012
  94 SDCR_D2:        .long   0x00000812      /* refresh */
  95 RTCSR_D:        .long   0xA55A0008      /* 1/4, once */
  96 RTCNT_D:        .long   0xA55A005D      /* count 93 */
  97 RTCOR_D:        .long   0xa55a005d      /* count 93 */
  98 /* mode register CL2, burst read and SINGLE WRITE */
  99 SDMR3_D:        .long   0x440
 100
 101 /*
 102  * Registers
 103  */
 104
 105 FRQCR_A:        .long   0xA415FF80
 106 WTCNT_A:        .long   0xA415FF84
 107 WTCSR_A:        .long   0xA415FF86
 108
 109 #define BSC_BASE        0xA4FD0000
 110 CS0BCR_A:       .long   BSC_BASE + 0x04
 111 CS3BCR_A:       .long   BSC_BASE + 0x0C
 112 CS0WCR_A:       .long   BSC_BASE + 0x24
 113 CS3WCR_A:       .long   BSC_BASE + 0x2C
 114 SDCR_A:         .long   BSC_BASE + 0x44
 115 RTCSR_A:        .long   BSC_BASE + 0x48
 116 RTCNT_A:        .long   BSC_BASE + 0x4C
 117 RTCOR_A:        .long   BSC_BASE + 0x50
 118 SDMR3_A:        .long   BSC_BASE + 0x5000