board/ms7750se/lowlevel_init.S

   1 /*
   2  modified from SH-IPL+g
   3  Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
   4
   5  Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
   6
   7  Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
   8
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26 */
  27
  28 #include <config.h>
  29 #include <version.h>
  30
  31 #include <asm/processor.h>
  32 #include <asm/macro.h>
  33
  34 #ifdef CONFIG_CPU_SH7751
  35 #define BCR2_D_VALUE    0x2FFC          /* Area 1-6 width: 32/32/32/32/32/16 */
  36 #define WCR1_D_VALUE    0x02770771      /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
  37 #ifdef CONFIG_MARUBUN_PCCARD
  38 #define WCR2_D_VALUE    0xFFFE4FE7      /* A6:15 A6B:7 A5:15 A5B:7 A4:15
  39                                            A3:2  A2:15 A1:15 A0:6  A0B:7  */
  40 #else /* CONFIG_MARUBUN_PCCARD */
  41 #define WCR2_D_VALUE    0x7FFE4FE7      /* A6:3  A6B:7 A5:15 A5B:7 A4:15
  42                                            A3:2  A2:15 A1:15 A0:6  A0B:7  */
  43 #endif /* CONFIG_MARUBUN_PCCARD */
  44 #define WCR3_D_VALUE    0x01777771      /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
  45                                            A2: 1-3 A1: 1-3 A0: 0-1 */
  46 #define RTCOR_D_VALUE   0xA50D          /* Write code A5, data 0D (~15us?) */
  47 #define SDMR3_ADDRESS   0xFF940088      /* SDMR3 address on 32-bit bus */
  48 #define MCR_D1_VALUE    0x100901B4      /* SDRAM 32-bit, CAS/RAS Refresh, .. */
  49 #define MCR_D2_VALUE    0x500901B4      /* Same w/MRSET now 1 (mode reg cmd) */
  50 #else /* CONFIG_CPU_SH7751 */
  51 #define BCR2_D_VALUE    0x2E3C          /* Area 1-6 width: 32/32/64/16/32/16 */
  52 #define WCR1_D_VALUE    0x02720777      /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
  53 #define WCR2_D_VALUE    0xFFFE4FFF      /* A6:15 A6B:7 A5:15 A5B:7 A4:15
  54                                            A3:2  A2:15 A1:15 A0:15 A0B:7  */
  55 #define WCR3_D_VALUE    0x01717771      /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
  56                                            A2: 1-3 A1: 1-3 A0: 0-1 */
  57 #define RTCOR_D_VALUE   0xA510          /* Write code A5, data 10 (~15us?) */
  58 #define SDMR3_ADDRESS   0xFF940110      /* SDMR3 address on 64-bit bus */
  59 #define MCR_D1_VALUE    0x8801001C      /* SDRAM 64-bit, CAS/RAS Refresh, .. */
  60 #define MCR_D2_VALUE    0xC801001C      /* Same w/MRSET now 1 (mode reg cmd) */
  61 #endif /* CONFIG_CPU_SH7751 */
  62
  63         .global lowlevel_init
  64         .text
  65         .align  2
  66
  67 lowlevel_init:
  68
  69         write32 CCR_A, CCR_D_DISABLE
  70
  71 init_bsc:
  72         write16 FRQCR_A, FRQCR_D
  73
  74         write32 BCR1_A, BCR1_D
  75
  76         write16 BCR2_A, BCR2_D
  77
  78         write32 WCR1_A, WCR1_D
  79
  80         write32 WCR2_A, WCR2_D
  81
  82         write32 WCR3_A, WCR3_D
  83
  84         write32 MCR_A, MCR_D1
  85
  86         /* Set SDRAM mode */
  87         write8  SDMR3_A, SDMR3_D
  88
  89         ! Do you need PCMCIA setting?
  90         ! If so, please add the lines here...
  91
  92         write16 RTCNT_A, RTCNT_D
  93
  94         write16 RTCOR_A, RTCOR_D
  95
  96         write16 RTCSR_A, RTCSR_D
  97
  98         write16 RFCR_A, RFCR_D
  99
 100         /* Wait DRAM refresh 30 times */
 101         mov     #30, r3
 102 1:
 103         mov.w   @r1, r0
 104         extu.w  r0, r2
 105         cmp/hi  r3, r2
 106         bf      1b
 107
 108         write32 MCR_A, MCR_D2
 109
 110         /* Set SDRAM mode */
 111         write8  SDMR3_A, SDMR3_D
 112
 113         rts
 114         nop
 115
 116         .align  2
 117
 118 CCR_A:           .long  CCR
 119 CCR_D_DISABLE:  .long   0x0808
 120 FRQCR_A:        .long   FRQCR
 121 FRQCR_D:
 122 #ifdef CONFIG_CPU_TYPE_R
 123                 .word   0x0e1a  /* 12:3:3 */
 124 #else   /* CONFIG_CPU_TYPE_R */
 125 #ifdef CONFIG_GOOD_SESH4
 126                 .word   0x00e13 /* 6:2:1 */
 127 #else
 128                 .word   0x00e23 /* 6:1:1 */
 129 #endif
 130 .align 2
 131 #endif  /* CONFIG_CPU_TYPE_R */
 132
 133 BCR1_A:         .long   BCR1
 134 BCR1_D:         .long   0x00000008      /* Area 3 SDRAM */
 135 BCR2_A:         .long   BCR2
 136 BCR2_D:         .long   BCR2_D_VALUE    /* Bus width settings */
 137 WCR1_A:         .long   WCR1
 138 WCR1_D:         .long   WCR1_D_VALUE    /* Inter-area or turnaround wait states */
 139 WCR2_A:         .long   WCR2
 140 WCR2_D:         .long   WCR2_D_VALUE    /* Per-area access and burst wait states */
 141 WCR3_A:         .long   WCR3
 142 WCR3_D:         .long   WCR3_D_VALUE    /* Address setup and data hold cycles */
 143 RTCSR_A:        .long   RTCSR
 144 RTCSR_D:        .word   0xA518          /* RTCSR Write Code A5h Data 18h */
 145 .align 2
 146 RTCNT_A:        .long   RTCNT
 147 RTCNT_D:        .word   0xA500          /* RTCNT Write Code A5h Data 00h */
 148 .align 2
 149 RTCOR_A:        .long   RTCOR
 150 RTCOR_D:        .word   RTCOR_D_VALUE   /* Set refresh time (about 15us) */
 151 .align 2
 152 SDMR3_A:        .long   SDMR3_ADDRESS
 153 SDMR3_D:        .long   0x00
 154 MCR_A:          .long   MCR
 155 MCR_D1:         .long   MCR_D1_VALUE
 156 MCR_D2:         .long   MCR_D2_VALUE
 157 RFCR_A:         .long   RFCR
 158 RFCR_D:         .word   0xA400          /* RFCR Write Code A4h Data 00h */
 159 .align 2