board/mvblue/mvblue.c

   1 /*
   2  * GNU General Public License for more details.
   3  *
   4  * MATRIX Vision GmbH / June 2002-Nov 2003
   5  * Andre Schwarz
   6  */
   7
   8 #include <common.h>
   9 #include <mpc824x.h>
  10 #include <asm/io.h>
  11 #include <ns16550.h>
  12
  13 #ifdef CONFIG_PCI
  14 #include <pci.h>
  15 #endif
  16
  17 u32 get_BoardType (void);
  18
  19 #define PCI_CONFIG(b,d,f,r)    cpu_to_le32(0x80000000 | ((b&0xff)<<16) \
  20                                                       | ((d&0x1f)<<11) \
  21                                                       | ((f&0x7)<<7)   \
  22                                                       | (r&0xfc) )
  23
  24 int mv_pci_read (int bus, int dev, int func, int reg)
  25 {
  26         *(u32 *) (0xfec00cf8) = PCI_CONFIG (bus, dev, func, reg);
  27         asm ("sync");
  28         return cpu_to_le32 (*(u32 *) (0xfee00cfc));
  29 }
  30
  31 u32 get_BoardType ()
  32 {
  33         return (mv_pci_read (0, 0xe, 0, 0) == 0x06801095 ? 0 : 1);
  34 }
  35
  36 void init_2nd_DUART (void)
  37 {
  38         NS16550_t console = (NS16550_t) CFG_NS16550_COM2;
  39         int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE;
  40
  41         *(u8 *) (0xfc004511) = 0x1;
  42         NS16550_init (console, clock_divisor);
  43 }
  44 void hw_watchdog_reset (void)
  45 {
  46         if (get_BoardType () == 0) {
  47                 *(u32 *) (0xff000005) = 0;
  48                 asm ("sync");
  49         }
  50 }
  51 int checkboard (void)
  52 {
  53         DECLARE_GLOBAL_DATA_PTR;
  54         ulong busfreq = get_bus_freq (0);
  55         char buf[32];
  56         u32 BoardType = get_BoardType ();
  57         char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" };
  58         char *p;
  59         bd_t *bd = gd->bd;
  60
  61         hw_watchdog_reset ();
  62
  63         printf ("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION);
  64         printf ("       Found %s running at %s MHz memory clock.\n",
  65                 BoardName[BoardType], strmhz (buf, busfreq));
  66
  67         init_2nd_DUART ();
  68
  69         if ((p = getenv ("console_nr")) != NULL) {
  70                 unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3;
  71
  72                 bd->bi_baudrate &= ~3;
  73                 bd->bi_baudrate |= con_nr & 3;
  74         }
  75         return 0;
  76 }
  77
  78 long int initdram (int board_type)
  79 {
  80         long size;
  81         long new_bank0_end;
  82         long mear1;
  83         long emear1;
  84
  85         size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
  86
  87         new_bank0_end = size - 1;
  88         mear1 = mpc824x_mpc107_getreg(MEAR1);
  89         emear1 = mpc824x_mpc107_getreg(EMEAR1);
  90         mear1 = (mear1  & 0xFFFFFF00) |
  91                 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
  92         emear1 = (emear1 & 0xFFFFFF00) |
  93                 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
  94         mpc824x_mpc107_setreg(MEAR1,  mear1);
  95         mpc824x_mpc107_setreg(EMEAR1, emear1);
  96
  97         return (size);
  98 }
  99
 100 /* ------------------------------------------------------------------------- */
 101 u8 *dhcp_vendorex_prep (u8 * e)
 102 {
 103         char *ptr;
 104
 105         /* DHCP vendor-class-identifier = 60 */
 106         if ((ptr = getenv ("dhcp_vendor-class-identifier"))) {
 107                 *e++ = 60;
 108                 *e++ = strlen (ptr);
 109                 while (*ptr)
 110                         *e++ = *ptr++;
 111         }
 112         /* my DHCP_CLIENT_IDENTIFIER = 61 */
 113         if ((ptr = getenv ("dhcp_client_id"))) {
 114                 *e++ = 61;
 115                 *e++ = strlen (ptr);
 116                 while (*ptr)
 117                         *e++ = *ptr++;
 118         }
 119         return e;
 120 }
 121
 122 u8 *dhcp_vendorex_proc (u8 * popt)
 123 {
 124         return NULL;
 125 }
 126
 127 /* ------------------------------------------------------------------------- */
 128
 129 /*
 130  * Initialize PCI Devices
 131  */
 132 #ifdef CONFIG_PCI
 133 void pci_mvblue_clear_base (struct pci_controller *hose, pci_dev_t dev)
 134 {
 135         u32 cnt;
 136
 137         printf ("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV (dev),
 138                 PCI_FUNC (dev));
 139         for (cnt = 0; cnt < 6; cnt++)
 140                 pci_hose_write_config_dword (hose, dev, 0x10 + (4 * cnt),
 141                                              0x0);
 142         printf ("done\n");
 143 }
 144
 145 void duart_setup (u32 base, u16 divisor)
 146 {
 147         printf ("duart setup ...");
 148         out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x80);
 149         out_8 ((u8 *) (CFG_ISA_IO + base + 0), divisor & 0xff);
 150         out_8 ((u8 *) (CFG_ISA_IO + base + 1), divisor >> 8);
 151         out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x03);
 152         out_8 ((u8 *) (CFG_ISA_IO + base + 4), 0x03);
 153         out_8 ((u8 *) (CFG_ISA_IO + base + 2), 0x07);
 154         printf ("done\n");
 155 }
 156
 157 void pci_mvblue_fixup_irq_behind_bridge (struct pci_controller *hose,
 158                                          pci_dev_t bridge, unsigned char irq)
 159 {
 160         pci_dev_t d;
 161         unsigned char bus;
 162         unsigned short vendor, class;
 163
 164         pci_hose_read_config_byte (hose, bridge, PCI_SECONDARY_BUS, &bus);
 165         for (d = PCI_BDF (bus, 0, 0);
 166              d < PCI_BDF (bus, PCI_MAX_PCI_DEVICES - 1,
 167                           PCI_MAX_PCI_FUNCTIONS - 1);
 168              d += PCI_BDF (0, 0, 1)) {
 169                 pci_hose_read_config_word (hose, d, PCI_VENDOR_ID, &vendor);
 170                 if (vendor != 0xffff && vendor != 0x0000) {
 171                         pci_hose_read_config_word (hose, d, PCI_CLASS_DEVICE,
 172                                                    &class);
 173                         if (class == PCI_CLASS_BRIDGE_PCI)
 174                                 pci_mvblue_fixup_irq_behind_bridge (hose, d,
 175                                                                     irq);
 176                         else
 177                                 pci_hose_write_config_byte (hose, d,
 178                                                             PCI_INTERRUPT_LINE,
 179                                                             irq);
 180                 }
 181         }
 182 }
 183
 184 #define MV_MAX_PCI_BUSSES       3
 185 #define SLOT0_IRQ       3
 186 #define SLOT1_IRQ       4
 187 void pci_mvblue_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
 188 {
 189         unsigned char line = 0xff;
 190         unsigned short class;
 191
 192         if (PCI_BUS (dev) == 0) {
 193                 switch (PCI_DEV (dev)) {
 194                 case 0xd:
 195                         if (get_BoardType () == 0) {
 196                                 line = 1;
 197                         } else
 198                                 /* mvBL */
 199                                 line = 2;
 200                         break;
 201                 case 0xe:
 202                         /* mvBB: IDE */
 203                         line = 2;
 204                         pci_hose_write_config_byte (hose, dev, 0x8a, 0x20);
 205                         break;
 206                 case 0xf:
 207                         /* mvBB: Slot0 (Grabber) */
 208                         pci_hose_read_config_word (hose, dev,
 209                                                    PCI_CLASS_DEVICE, &class);
 210                         if (class == PCI_CLASS_BRIDGE_PCI) {
 211                                 pci_mvblue_fixup_irq_behind_bridge (hose, dev,
 212                                                                     SLOT0_IRQ);
 213                                 line = 0xff;
 214                         } else
 215                                 line = SLOT0_IRQ;
 216                         break;
 217                 case 0x10:
 218                         /* mvBB: Slot1 */
 219                         pci_hose_read_config_word (hose, dev,
 220                                                    PCI_CLASS_DEVICE, &class);
 221                         if (class == PCI_CLASS_BRIDGE_PCI) {
 222                                 pci_mvblue_fixup_irq_behind_bridge (hose, dev,
 223                                                                     SLOT1_IRQ);
 224                                 line = 0xff;
 225                         } else
 226                                 line = SLOT1_IRQ;
 227                         break;
 228                 default:
 229                         printf ("***pci_scan: illegal dev = 0x%08x\n",
 230                                 PCI_DEV (dev));
 231                         line = 0xff;
 232                         break;
 233                 }
 234                 pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE,
 235                                             line);
 236         }
 237 }
 238
 239 struct pci_controller hose = {
 240         fixup_irq:pci_mvblue_fixup_irq
 241 };
 242
 243 void pci_init_board (void)
 244 {
 245         pci_mpc824x_init (&hose);
 246 }
 247 #endif