board/mx1ads/mx1ads.c

   1 /*
   2  * board/mx1ads/mx1ads.c
   3  *
   4  * (c) Copyright 2004
   5  * Techware Information Technology, Inc.
   6  * http://www.techware.com.tw/
   7  *
   8  * Ming-Len Wu <minglen_wu@techware.com.tw>
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26
  27 #include <common.h>
  28 #include <mc9328.h>
  29
  30 /* ------------------------------------------------------------------------- */
  31
  32 #define FCLK_SPEED 1
  33
  34 #if FCLK_SPEED==0               /* Fout = 203MHz, Fin = 12MHz for Audio */
  35 #define M_MDIV  0xC3
  36 #define M_PDIV  0x4
  37 #define M_SDIV  0x1
  38 #elif FCLK_SPEED==1             /* Fout = 202.8MHz */
  39 #define M_MDIV  0xA1
  40 #define M_PDIV  0x3
  41 #define M_SDIV  0x1
  42 #endif
  43
  44 #define USB_CLOCK 1
  45
  46 #if USB_CLOCK==0
  47 #define U_M_MDIV        0xA1
  48 #define U_M_PDIV        0x3
  49 #define U_M_SDIV        0x1
  50 #elif USB_CLOCK==1
  51 #define U_M_MDIV        0x48
  52 #define U_M_PDIV        0x3
  53 #define U_M_SDIV        0x2
  54 #endif
  55
  56 #if 0
  57
  58 static inline void delay (unsigned long loops) {
  59         __asm__ volatile ("1:\n"
  60           "subs %0, %1, #1\n"
  61           "bne 1b":"=r" (loops):"0" (loops));
  62 }
  63
  64 #endif
  65
  66 /*
  67  * Miscellaneous platform dependent initialisations
  68  */
  69
  70
  71 void SetAsynchMode(void) {
  72         __asm__ (
  73                 "mrc p15,0,r0,c1,c0,0 \n"
  74                 "mov r2, #0xC0000000 \n"
  75                 "orr r0,r2,r0 \n"
  76                 "mcr p15,0,r0,c1,c0,0 \n"
  77         );
  78 }
  79
  80 static u32 mc9328sid;
  81
  82 int board_init (void) {
  83
  84         DECLARE_GLOBAL_DATA_PTR;
  85
  86         volatile unsigned int  tmp;
  87
  88         mc9328sid       = MX1_SIDR;
  89
  90         MX1_GPCR        = 0x000003AB;           /* I/O pad driving strength     */
  91
  92 /*      MX1_CS1U        = 0x00000A00;   */      /* SRAM initialization          */
  93 /*      MX1_CS1L        = 0x11110601;   */
  94
  95         MX1_MPCTL0      = 0x04632410;   /* setting for 150 MHz MCU PLL CLK      */
  96
  97 /*      MX1_MPCTL0      = 0x003f1437;   */ /* setting for 192 MHz MCU PLL CLK   */
  98
  99 /* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
 100  * BCLK divider to 2 (i.e. BCLK to 48 MHz)
 101  */
 102         MX1_CSCR        = 0xAF000403;
 103
 104         MX1_CSCR        |= 0x00200000;          /* Trigger the restart bit(bit 21)      */
 105         MX1_CSCR        &= 0xFFFF7FFF;          /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
 106
 107 /* setup cs4 for cs8900 ethernet */
 108
 109         MX1_CS4U        = 0x00000F00;   /* Initialize CS4 for CS8900 ethernet   */
 110         MX1_CS4L        = 0x00001501;
 111
 112         MX1_GIUS_A      &= 0xFF3FFFFF;
 113         MX1_GPR_A       &= 0xFF3FFFFF;
 114
 115         tmp = *(unsigned int *)(0x1500000C);
 116         tmp = *(unsigned int *)(0x1500000C);
 117
 118 /* setup timer 1 as system timer        */
 119
 120         MX1_TPRER1      = 0x1f;         /* divide by 32                 */
 121         MX1_TCTL1       = 0x19;         /* clock in from 32k Osc.       */
 122
 123
 124         SetAsynchMode();
 125
 126         gd->bd->bi_arch_number = 160;   /* Arch number of MX1ADS Board          */
 127
 128         gd->bd->bi_boot_params = 0x08000100;    /* adress of boot parameters    */
 129
 130         icache_enable();
 131         dcache_enable();
 132
 133 /* set PERCLKs                          */
 134         MX1_PCDR = 0x00000055;          /* set PERCLKS                          */
 135
 136 /* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
 137  * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
 138  * all sources selected as normal interrupt
 139  */
 140         MX1_INTTYPEH = 0;
 141         MX1_INTTYPEL = 0;
 142
 143         return 0;
 144 }
 145
 146
 147 int board_late_init(void) {
 148
 149         setenv("stdout", "serial");
 150         setenv("stderr", "serial");
 151
 152         switch  (mc9328sid) {
 153                 case 0x0005901d :
 154                         printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",mc9328sid);
 155                         break;
 156                 case 0x04d4c01d :
 157                         printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",mc9328sid);
 158                         break;
 159                 case 0x00d4c01d :
 160                         printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",mc9328sid);
 161                         break;
 162
 163                 default :
 164                         printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid);
 165                         break;
 166
 167         }
 168
 169         return 0;
 170 }
 171
 172
 173 int dram_init (void) {
 174         DECLARE_GLOBAL_DATA_PTR;
 175
 176         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 177         gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
 178
 179         return 0;
 180 }