board/netstal/hcu5/hcu5.c

   1 /*
   2  *(C) Copyright 2005-2008 Netstal Maschinen AG
   3  *    Niklaus Giger (Niklaus.Giger@netstal.com)
   4  *
   5  *    This source code is free software; you can redistribute it
   6  *    and/or modify it in source code form under the terms of the GNU
   7  *    General Public License as published by the Free Software
   8  *    Foundation; either version 2 of the License, or (at your option)
   9  *    any later version.
  10  *
  11  *    This program is distributed in the hope that it will be useful,
  12  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *    GNU General Public License for more details.
  15  *
  16  *    You should have received a copy of the GNU General Public License
  17  *    along with this program; if not, write to the Free Software
  18  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  19  */
  20
  21 #include <common.h>
  22 #include <asm/processor.h>
  23 #include <asm/ppc440.h>
  24 #include <asm/io.h>
  25 #include <asm/4xx_pci.h>
  26
  27 #include  "../common/nm.h"
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
  32
  33 #undef BOOTSTRAP_OPTION_A_ACTIVE
  34
  35 #define SDR0_CP440              0x0180
  36
  37 #define SYSTEM_RESET            0x30000000
  38 #define CHIP_RESET              0x20000000
  39
  40 #define SDR0_ECID0              0x0080
  41 #define SDR0_ECID1              0x0081
  42 #define SDR0_ECID2              0x0082
  43 #define SDR0_ECID3              0x0083
  44
  45 #define SYS_IO_ADDRESS                  (CONFIG_SYS_CS_2 + 0x00e00000)
  46 #define SYS_SLOT_ADDRESS                (CONFIG_SYS_CPLD + 0x00400000)
  47 #define HCU_DIGITAL_IO_REGISTER (CONFIG_SYS_CPLD + 0x0500000)
  48 #define HCU_SW_INSTALL_REQUESTED        0x10
  49
  50 /*
  51  * This function is run very early, out of flash, and before devices are
  52  * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
  53  * of being in the init_sequence array.
  54  *
  55  * The SDRAM has been initialized already -- start.S:start called
  56  * init.S:init_sdram early on -- but it is not yet being used for
  57  * anything, not even stack. So be careful.
  58  */
  59
  60 int board_early_init_f(void)
  61 {
  62
  63 #ifdef BOOTSTRAP_OPTION_A_ACTIVE
  64         /* Booting with Bootstrap Option A
  65          * First boot, with CPR0_ICFG_RLI_MASK == 0
  66          * no we setup varios boot strapping register,
  67          * then we do reset the PPC440 using a chip reset
  68          * Unfortunately, we cannot use this option, as Nto1 is not set
  69          * with Bootstrap Option A and cannot be changed later on by SW
  70          * There are no other possible boostrap options with a 8 bit ROM
  71          * See Errata (Version 1.04) CHIP_9
  72          */
  73
  74         u32 cpr0icfg;
  75         u32 dbcr;
  76
  77         mfcpr(CPR0_ICFG, cpr0icfg);
  78         if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) {
  79                 mtcpr(CPR0_MALD,   0x02000000);
  80                 mtcpr(CPR0_OPBD,   0x02000000);
  81                 mtcpr(CPR0_PERD,   0x05000000);  /* 1:5 */
  82                 mtcpr(CPR0_PLLC,   0x40000238);
  83                 mtcpr(CPR0_PLLD,   0x01010414);
  84                 mtcpr(CPR0_PRIMAD, 0x01000000);
  85                 mtcpr(CPR0_PRIMBD, 0x01000000);
  86                 mtcpr(CPR0_SPCID,  0x03000000);
  87                 mtsdr(SDR0_PFC0,   0x00003E00);  /* [CTE] = 0 */
  88                 mtsdr(SDR0_CP440,  0x0EAAEA02);  /* [Nto1] = 1*/
  89                 mtcpr(CPR0_ICFG,   cpr0icfg | CPR0_ICFG_RLI_MASK);
  90
  91                 /*
  92                  * Initiate system reset in debug control register DBCR
  93                  */
  94                 dbcr = mfspr(SPRN_DBCR0);
  95                 mtspr(SPRN_DBCR0, dbcr | CHIP_RESET);
  96         }
  97         mtsdr(SDR0_CP440, 0x0EAAEA02);  /* [Nto1] = 1*/
  98 #endif
  99         mtdcr(EBC0_CFGADDR, EBC0_CFG);
 100         mtdcr(EBC0_CFGDATA, 0xb8400000);
 101
 102         /*
 103          * Setup the GPIO pins
 104          */
 105         out32(GPIO0_OR, 0x00000000);
 106         out32(GPIO0_TCR, 0x7C2FF1CF);
 107         out32(GPIO0_OSRL, 0x40055000);
 108         out32(GPIO0_OSRH, 0x00000000);
 109         out32(GPIO0_TSRL, 0x40055000);
 110         out32(GPIO0_TSRH, 0x00000400);
 111         out32(GPIO0_ISR1L, 0x40000000);
 112         out32(GPIO0_ISR1H, 0x00000000);
 113         out32(GPIO0_ISR2L, 0x00000000);
 114         out32(GPIO0_ISR2H, 0x00000000);
 115         out32(GPIO0_ISR3L, 0x00000000);
 116         out32(GPIO0_ISR3H, 0x00000000);
 117
 118         out32(GPIO1_OR, 0x00000000);
 119         out32(GPIO1_TCR, 0xC6007FFF);
 120         out32(GPIO1_OSRL, 0x00140000);
 121         out32(GPIO1_OSRH, 0x00000000);
 122         out32(GPIO1_TSRL, 0x00000000);
 123         out32(GPIO1_TSRH, 0x00000000);
 124         out32(GPIO1_ISR1L, 0x05415555);
 125         out32(GPIO1_ISR1H, 0x40000000);
 126         out32(GPIO1_ISR2L, 0x00000000);
 127         out32(GPIO1_ISR2H, 0x00000000);
 128         out32(GPIO1_ISR3L, 0x00000000);
 129         out32(GPIO1_ISR3H, 0x00000000);
 130
 131         /*
 132          * Setup the interrupt controller polarities, triggers, etc.
 133          */
 134         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
 135         mtdcr(UIC0ER, 0x00000000);      /* disable all */
 136         mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
 137         mtdcr(UIC0PR, 0xfffff7ff);      /* per ref-board manual */
 138         mtdcr(UIC0TR, 0x00000000);      /* per ref-board manual */
 139         mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
 140         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
 141
 142         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 143         mtdcr(UIC1ER, 0x00000000);      /* disable all */
 144         mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
 145         mtdcr(UIC1PR, 0xffffffff);      /* per ref-board manual */
 146         mtdcr(UIC1TR, 0x00000000);      /* per ref-board manual */
 147         mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
 148         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 149
 150         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
 151         mtdcr(UIC2ER, 0x00000000);      /* disable all */
 152         mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
 153         mtdcr(UIC2PR, 0xffffffff);      /* per ref-board manual */
 154         mtdcr(UIC2TR, 0x00000000);      /* per ref-board manual */
 155         mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
 156         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
 157         mtsdr(SDR0_PFC0, 0x00003E00);   /* Pin function:  */
 158         mtsdr(SDR0_PFC1, 0x00848000);   /* Pin function: UART0 has 4 pins */
 159
 160         /* setup BOOT FLASH */
 161         mtsdr(SDR0_CUST0, 0xC0082350);
 162
 163         return 0;
 164 }
 165
 166 #ifdef CONFIG_BOARD_PRE_INIT
 167 int board_pre_init(void)
 168 {
 169         return board_early_init_f();
 170 }
 171
 172 #endif
 173
 174 int sys_install_requested(void)
 175 {
 176         u16 *ioValuePtr = (u16 *)HCU_DIGITAL_IO_REGISTER;
 177         return (in_be16(ioValuePtr) & HCU_SW_INSTALL_REQUESTED) != 0;
 178 }
 179
 180 int checkboard(void)
 181 {
 182         u16 *hwVersReg    = (u16 *) HCU_HW_VERSION_REGISTER;
 183         u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
 184         u16 generation = in_be16(boardVersReg) & 0xf0;
 185         u16 index      = in_be16(boardVersReg) & 0x0f;
 186         u32 ecid0, ecid1, ecid2, ecid3;
 187
 188         nm_show_print(generation, index, in_be16(hwVersReg) & 0xff);
 189         mfsdr(SDR0_ECID0, ecid0);
 190         mfsdr(SDR0_ECID1, ecid1);
 191         mfsdr(SDR0_ECID2, ecid2);
 192         mfsdr(SDR0_ECID3, ecid3);
 193
 194         printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
 195
 196         return 0;
 197 }
 198
 199 u32 hcu_led_get(void)
 200 {
 201         return in16(SYS_IO_ADDRESS) & 0x3f;
 202 }
 203
 204 /*
 205  * hcu_led_set  value to be placed into the LEDs (max 6 bit)
 206  */
 207 void hcu_led_set(u32 value)
 208 {
 209         out16(SYS_IO_ADDRESS, value);
 210 }
 211
 212 /*
 213  * get_serial_number
 214  */
 215 u32 get_serial_number(void)
 216 {
 217         u32 *serial = (u32 *)CONFIG_SYS_FLASH_BASE;
 218
 219         if (in_be32(serial) == 0xffffffff)
 220                 return 0;
 221
 222         return in_be32(serial);
 223 }
 224
 225
 226 /*
 227  * hcu_get_slot
 228  */
 229 u32 hcu_get_slot(void)
 230 {
 231         u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
 232         return in_be16(slot) & 0x7f;
 233 }
 234
 235
 236 /*
 237  * misc_init_r.
 238  */
 239 int misc_init_r(void)
 240 {
 241         unsigned long usb2d0cr = 0;
 242         unsigned long usb2phy0cr, usb2h0cr = 0;
 243         unsigned long sdr0_pfc1;
 244
 245 #ifdef CONFIG_ENV_IS_IN_FLASH
 246         /* Monitor protection ON by default */
 247         (void)flash_protect(FLAG_PROTECT_SET,
 248                             -CONFIG_SYS_MONITOR_LEN,
 249                             0xffffffff,
 250                             &flash_info[0]);
 251
 252 #ifdef CONFIG_ENV_ADDR_REDUND
 253         /* Env protection ON by default */
 254         (void)flash_protect(FLAG_PROTECT_SET,
 255                             CONFIG_ENV_ADDR_REDUND,
 256                             CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
 257                             &flash_info[0]);
 258 #endif
 259 #endif
 260
 261         /*
 262          * USB stuff...
 263          */
 264
 265         /* SDR Setting */
 266         mfsdr(SDR0_PFC1, sdr0_pfc1);
 267         mfsdr(SDR0_USB2D0CR, usb2d0cr);
 268         mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 269         mfsdr(SDR0_USB2H0CR, usb2h0cr);
 270
 271         usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 272         usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;       /*0*/
 273         usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 274         usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;    /*1*/
 275         usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 276         usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;         /*0*/
 277         usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 278         usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;          /*1*/
 279         usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 280         usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;          /*1*/
 281
 282         /* An 8-bit/60MHz interface is the only possible alternative
 283          *  when connecting the Device to the PHY
 284          */
 285         usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 286         usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;        /*1*/
 287
 288         /* To enable the USB 2.0 Device function through the UTMI interface */
 289         usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 290         usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;          /*1*/
 291
 292         sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 293         sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;                /*0*/
 294
 295         mtsdr(SDR0_PFC1, sdr0_pfc1);
 296         mtsdr(SDR0_USB2D0CR, usb2d0cr);
 297         mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 298         mtsdr(SDR0_USB2H0CR, usb2h0cr);
 299
 300         /*clear resets*/
 301         udelay(1000);
 302         mtsdr(SDR0_SRST1, 0x00000000);
 303         udelay(1000);
 304         mtsdr(SDR0_SRST0, 0x00000000);
 305         printf("USB:   Host(int phy) Device(ext phy)\n");
 306
 307         common_misc_init_r();
 308         set_params_for_sw_install( sys_install_requested(), "hcu5" );
 309         /* We cannot easily enable trace before, as there are other
 310          * routines messing around with sdr0_pfc1. And I do not need it.
 311          */
 312         if (mfspr(SPRN_DBCR0) & 0x80000000) {
 313                 /* External debugger alive
 314                  * enable trace facilty for Lauterbach
 315                  * CCR0[DTB]=0          Enable broadcast of trace information
 316                  * SDR0_PFC0[TRE]       Trace signals are enabled instead of
 317                  *                      GPIO49-63
 318                  */
 319                 mtspr(SPRN_CCR0, mfspr(SPRN_CCR0)  &~ (CCR0_DTB));
 320                 mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE);
 321         }
 322         return 0;
 323 }
 324 #ifdef CONFIG_PCI
 325 int board_with_pci(void)
 326 {
 327         u32 reg;
 328
 329         mfsdr(SDR0_PCI0, reg);
 330         return (reg & SDR0_XCR_PAE_MASK);
 331 }
 332
 333 /*
 334  *  pci_pre_init
 335  *
 336  *  This routine is called just prior to registering the hose and gives
 337  *  the board the opportunity to check things. Returning a value of zero
 338  *  indicates that things are bad & PCI initialization should be aborted.
 339  *
 340  *      Different boards may wish to customize the pci controller structure
 341  *      (add regions, override default access routines, etc) or perform
 342  *      certain pre-initialization actions.
 343  *
 344  */
 345 int pci_pre_init(struct pci_controller *hose)
 346 {
 347         unsigned long addr;
 348
 349         if (!board_with_pci()) { return 0; }
 350
 351         /*
 352          * Set priority for all PLB3 devices to 0.
 353          * Set PLB3 arbiter to fair mode.
 354          */
 355         mfsdr(SD0_AMP1, addr);
 356         mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
 357         addr = mfdcr(PLB3_ACR);
 358         mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */
 359
 360         /*
 361          * Set priority for all PLB4 devices to 0.
 362          */
 363         mfsdr(SD0_AMP0, addr);
 364         mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
 365         addr = mfdcr(PLB4_ACR) | 0xa0000000;    /* Was 0x8---- */
 366         mtdcr(PLB4_ACR, addr);  /* Sequoia */
 367
 368         /*
 369          * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
 370          * Workaround: Disable write pipelining to DDR SDRAM by setting
 371          * PLB0_ACR[WRP] = 0.
 372          */
 373         mtdcr(PLB0_ACR, 0);  /* PATCH HAB: WRITE PIPELINING OFF */
 374
 375         /* Segment1 */
 376         mtdcr(PLB1_ACR, 0);  /* PATCH HAB: WRITE PIPELINING OFF */
 377
 378         return board_with_pci();
 379 }
 380
 381 /*
 382  * Override weak default pci_master_init()
 383  */
 384 void pci_master_init(struct pci_controller *hose)
 385 {
 386         if (!board_with_pci())
 387                 return;
 388
 389         __pci_master_init(hose);
 390 }
 391 #endif   /* defined(CONFIG_PCI) */
 392
 393 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 394 void ft_board_setup(void *blob, bd_t *bd)
 395 {
 396         ft_cpu_setup(blob, bd);
 397
 398 }
 399 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
 400
 401 /*
 402  * Hardcoded flash setup:
 403  * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
 404  */
 405 ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
 406 {
 407         if (banknum == 0) {     /* non-CFI boot flash */
 408                 info->portwidth = 1;
 409                 info->chipwidth = 1;
 410                 info->interface = FLASH_CFI_X8;
 411                 return 1;
 412         } else
 413                 return 0;
 414 }