board/netstal/hcu5/hcu5.c

   1 /*
   2  *(C) Copyright 2005-2007 Netstal Maschinen AG
   3  *    Niklaus Giger (Niklaus.Giger@netstal.com)
   4  *
   5  *    This source code is free software; you can redistribute it
   6  *    and/or modify it in source code form under the terms of the GNU
   7  *    General Public License as published by the Free Software
   8  *    Foundation; either version 2 of the License, or (at your option)
   9  *    any later version.
  10  *
  11  *    This program is distributed in the hope that it will be useful,
  12  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *    GNU General Public License for more details.
  15  *
  16  *    You should have received a copy of the GNU General Public License
  17  *    along with this program; if not, write to the Free Software
  18  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  19  */
  20
  21 #include <common.h>
  22 #include <asm/processor.h>
  23 #include <ppc440.h>
  24 #include <asm/mmu.h>
  25 #include <net.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 void hcu_led_set(u32 value);
  30
  31 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
  32
  33 #undef BOOTSTRAP_OPTION_A_ACTIVE
  34
  35 #define SDR0_CP440              0x0180
  36
  37 #define SYSTEM_RESET            0x30000000
  38 #define CHIP_RESET              0x20000000
  39
  40 #define SDR0_ECID0              0x0080
  41 #define SDR0_ECID1              0x0081
  42 #define SDR0_ECID2              0x0082
  43 #define SDR0_ECID3              0x0083
  44
  45 #define SYS_IO_ADDRESS          (CFG_CS_2 + 0x00e00000)
  46 #define SYS_SLOT_ADDRESS                (CFG_CPLD + 0x00400000)
  47
  48 #define DEFAULT_ETH_ADDR  "ethaddr"
  49 /* ethaddr for first or etha1ddr for second ethernet */
  50
  51 enum {
  52         /* HW_GENERATION_HCU1 is no longer supported */
  53         HW_GENERATION_HCU2  = 0x10,
  54         HW_GENERATION_HCU3  = 0x10,
  55         HW_GENERATION_HCU4  = 0x20,
  56         HW_GENERATION_HCU5  = 0x30,
  57         HW_GENERATION_MCU   = 0x08,
  58         HW_GENERATION_MCU20 = 0x0a,
  59         HW_GENERATION_MCU25 = 0x09,
  60 };
  61
  62
  63 /*
  64  * This function is run very early, out of flash, and before devices are
  65  * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
  66  * of being in the init_sequence array.
  67  *
  68  * The SDRAM has been initialized already -- start.S:start called
  69  * init.S:init_sdram early on -- but it is not yet being used for
  70  * anything, not even stack. So be careful.
  71  */
  72
  73 int board_early_init_f(void)
  74 {
  75         u32 reg;
  76
  77 #ifdef BOOTSTRAP_OPTION_A_ACTIVE
  78         /* Booting with Bootstrap Option A
  79          * First boot, with CPR0_ICFG_RLI_MASK == 0
  80          * no we setup varios boot strapping register,
  81          * then we do reset the PPC440 using a chip reset
  82          * Unfortunately, we cannot use this option, as Nto1 is not set
  83          * with Bootstrap Option A and cannot be changed later on by SW
  84          * There are no other possible boostrap options with a 8 bit ROM
  85          * See Errata (Version 1.04) CHIP_9
  86          */
  87
  88         u32 cpr0icfg;
  89         u32 dbcr;
  90
  91         mfcpr(CPR0_ICFG, cpr0icfg);
  92         if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) {
  93                 mtcpr(CPR0_MALD,   0x02000000);
  94                 mtcpr(CPR0_OPBD,   0x02000000);
  95                 mtcpr(CPR0_PERD,   0x05000000);  /* 1:5 */
  96                 mtcpr(CPR0_PLLC,   0x40000238);
  97                 mtcpr(CPR0_PLLD,   0x01010414);
  98                 mtcpr(CPR0_PRIMAD, 0x01000000);
  99                 mtcpr(CPR0_PRIMBD, 0x01000000);
 100                 mtcpr(CPR0_SPCID,  0x03000000);
 101                 mtsdr(SDR0_PFC0,   0x00003E00);  /* [CTE] = 0 */
 102                 mtsdr(SDR0_CP440,  0x0EAAEA02);  /* [Nto1] = 1*/
 103                 mtcpr(CPR0_ICFG,   cpr0icfg | CPR0_ICFG_RLI_MASK);
 104
 105                 /*
 106                  * Initiate system reset in debug control register DBCR
 107                  */
 108                 dbcr = mfspr(dbcr0);
 109                 mtspr(dbcr0, dbcr | CHIP_RESET);
 110         }
 111         mtsdr(SDR0_CP440, 0x0EAAEA02);  /* [Nto1] = 1*/
 112 #endif
 113         mtdcr(ebccfga, xbcfg);
 114         mtdcr(ebccfgd, 0xb8400000);
 115
 116         /*--------------------------------------------------------------------
 117          * Setup the GPIO pins
 118          *-------------------------------------------------------------------*/
 119         /* test-only: take GPIO init from pcs440ep ???? in config file */
 120         out32(GPIO0_OR, 0x00000000);
 121         out32(GPIO0_TCR, 0x7C2FF1CF);
 122         out32(GPIO0_OSRL, 0x40055000);
 123         out32(GPIO0_OSRH, 0x00000000);
 124         out32(GPIO0_TSRL, 0x40055000);
 125         out32(GPIO0_TSRH, 0x00000400);
 126         out32(GPIO0_ISR1L, 0x40000000);
 127         out32(GPIO0_ISR1H, 0x00000000);
 128         out32(GPIO0_ISR2L, 0x00000000);
 129         out32(GPIO0_ISR2H, 0x00000000);
 130         out32(GPIO0_ISR3L, 0x00000000);
 131         out32(GPIO0_ISR3H, 0x00000000);
 132
 133         out32(GPIO1_OR, 0x00000000);
 134         out32(GPIO1_TCR, 0xC6007FFF);
 135         out32(GPIO1_OSRL, 0x00140000);
 136         out32(GPIO1_OSRH, 0x00000000);
 137         out32(GPIO1_TSRL, 0x00000000);
 138         out32(GPIO1_TSRH, 0x00000000);
 139         out32(GPIO1_ISR1L, 0x05415555);
 140         out32(GPIO1_ISR1H, 0x40000000);
 141         out32(GPIO1_ISR2L, 0x00000000);
 142         out32(GPIO1_ISR2H, 0x00000000);
 143         out32(GPIO1_ISR3L, 0x00000000);
 144         out32(GPIO1_ISR3H, 0x00000000);
 145
 146         /*--------------------------------------------------------------------
 147          * Setup the interrupt controller polarities, triggers, etc.
 148          *-------------------------------------------------------------------*/
 149         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 150         mtdcr(uic0er, 0x00000000);      /* disable all */
 151         mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
 152         mtdcr(uic0pr, 0xfffff7ff);      /* per ref-board manual */
 153         mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
 154         mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
 155         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 156
 157         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 158         mtdcr(uic1er, 0x00000000);      /* disable all */
 159         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
 160         mtdcr(uic1pr, 0xffffffff);      /* per ref-board manual */
 161         mtdcr(uic1tr, 0x00000000);      /* per ref-board manual */
 162         mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
 163         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 164
 165         mtdcr(uic2sr, 0xffffffff);      /* clear all */
 166         mtdcr(uic2er, 0x00000000);      /* disable all */
 167         mtdcr(uic2cr, 0x00000000);      /* all non-critical */
 168         mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
 169         mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
 170         mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
 171         mtdcr(uic2sr, 0xffffffff);      /* clear all */
 172         mtsdr(sdr_pfc0, 0x00003E00);    /* Pin function:  */
 173         mtsdr(sdr_pfc1, 0x00848000);    /* Pin function: UART0 has 4 pins */
 174
 175         /* PCI arbiter enabled */
 176         mfsdr(sdr_pci0, reg);
 177         mtsdr(sdr_pci0, 0x80000000 | reg);
 178
 179         pci_pre_init(0);
 180
 181         /* setup BOOT FLASH */
 182         mtsdr(SDR0_CUST0, 0xC0082350);
 183
 184         return 0;
 185 }
 186
 187 #ifdef CONFIG_BOARD_PRE_INIT
 188 int board_pre_init(void)
 189 {
 190         return board_early_init_f();
 191 }
 192
 193 #endif
 194
 195 int checkboard(void)
 196 {
 197         unsigned int j;
 198         u16 *hwVersReg    = (u16 *) HCU_HW_VERSION_REGISTER;
 199         u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
 200         u16 generation = *boardVersReg & 0xf0;
 201         u16 index      = *boardVersReg & 0x0f;
 202         u32 ecid0, ecid1, ecid2, ecid3;
 203
 204         printf("Netstal Maschinen AG: ");
 205         if (generation == HW_GENERATION_HCU3)
 206                 printf("HCU3: index %d", index);
 207         else if (generation == HW_GENERATION_HCU4)
 208                 printf("HCU4: index %d", index);
 209         else if (generation == HW_GENERATION_HCU5)
 210                 printf("HCU5: index %d", index);
 211         printf(" HW 0x%02x\n", *hwVersReg & 0xff);
 212         mfsdr(SDR0_ECID0, ecid0);
 213         mfsdr(SDR0_ECID1, ecid1);
 214         mfsdr(SDR0_ECID2, ecid2);
 215         mfsdr(SDR0_ECID3, ecid3);
 216
 217         printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
 218         for (j = 0;j < 6; j++) {
 219                 hcu_led_set(1 << j);
 220                 udelay(200 * 1000);
 221         }
 222
 223         return 0;
 224 }
 225
 226 u32 hcu_led_get(void)
 227 {
 228         return in16(SYS_IO_ADDRESS) & 0x3f;
 229 }
 230
 231 /*---------------------------------------------------------------------------+
 232  * hcu_led_set  value to be placed into the LEDs (max 6 bit)
 233  *---------------------------------------------------------------------------*/
 234 void hcu_led_set(u32 value)
 235 {
 236         out16(SYS_IO_ADDRESS, value);
 237 }
 238
 239 /*---------------------------------------------------------------------------+
 240  * get_serial_number
 241  *---------------------------------------------------------------------------*/
 242 static u32 get_serial_number(void)
 243 {
 244         u32 *serial = (u32 *)CFG_FLASH_BASE;
 245
 246         if (*serial == 0xffffffff)
 247                 return 0;
 248
 249         return *serial;
 250 }
 251
 252
 253 /*---------------------------------------------------------------------------+
 254  * hcu_get_slot
 255  *---------------------------------------------------------------------------*/
 256 u32 hcu_get_slot(void)
 257 {
 258         u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
 259         return (*slot) & 0x7f;
 260 }
 261
 262
 263 /*---------------------------------------------------------------------------+
 264  * misc_init_r.
 265  *---------------------------------------------------------------------------*/
 266 int misc_init_r(void)
 267 {
 268         char *s = getenv(DEFAULT_ETH_ADDR);
 269         char *e;
 270         int i;
 271         u32 serial = get_serial_number();
 272         unsigned long usb2d0cr = 0;
 273         unsigned long usb2phy0cr, usb2h0cr = 0;
 274         unsigned long sdr0_pfc1;
 275
 276         for (i = 0; i < 6; ++i) {
 277                 gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
 278                 if (s)
 279                         s = (*e) ? e + 1 : e;
 280         }
 281
 282         if (gd->bd->bi_enetaddr[3] == 0 &&
 283             gd->bd->bi_enetaddr[4] == 0 &&
 284             gd->bd->bi_enetaddr[5] == 0) {
 285                 char ethaddr[22];
 286
 287                 /* Must be in sync with CONFIG_ETHADDR */
 288                 gd->bd->bi_enetaddr[0] = 0x00;
 289                 gd->bd->bi_enetaddr[1] = 0x60;
 290                 gd->bd->bi_enetaddr[2] = 0x13;
 291                 gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
 292                 gd->bd->bi_enetaddr[4] = (serial >>  8) & 0xff;
 293                 gd->bd->bi_enetaddr[5] = hcu_get_slot();
 294                 sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
 295                         gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
 296                         gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
 297                         gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
 298                 printf("%s: Setting eth %s serial 0x%x\n",  __FUNCTION__,
 299                        ethaddr, serial);
 300                 setenv(DEFAULT_ETH_ADDR, ethaddr);
 301         }
 302
 303         /* IP-Adress update */
 304         {
 305                 IPaddr_t ipaddr;
 306                 char *ipstring;
 307
 308                 ipstring = getenv("ipaddr");
 309                 if (ipstring == 0)
 310                         ipaddr = string_to_ip("172.25.1.99");
 311                 else
 312                         ipaddr = string_to_ip(ipstring);
 313                 if ((ipaddr & 0xff) != (32 + hcu_get_slot())) {
 314                         char tmp[22];
 315
 316                         ipaddr = (ipaddr & 0xffffff00) + 32 + hcu_get_slot();
 317                         ip_to_string (ipaddr, tmp);
 318                         printf("%s: enforce %s\n",  __FUNCTION__, tmp);
 319                         setenv("ipaddr", tmp);
 320                 }
 321         }
 322 #ifdef CFG_ENV_IS_IN_FLASH
 323         /* Monitor protection ON by default */
 324         (void)flash_protect(FLAG_PROTECT_SET,
 325                             -CFG_MONITOR_LEN,
 326                             0xffffffff,
 327                             &flash_info[0]);
 328
 329         /* Env protection ON by default */
 330         (void)flash_protect(FLAG_PROTECT_SET,
 331                             CFG_ENV_ADDR_REDUND,
 332                             CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
 333                             &flash_info[0]);
 334 #endif
 335
 336         /*
 337          * USB stuff...
 338          */
 339
 340         /* SDR Setting */
 341         mfsdr(SDR0_PFC1, sdr0_pfc1);
 342         mfsdr(SDR0_USB2D0CR, usb2d0cr);
 343         mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 344         mfsdr(SDR0_USB2H0CR, usb2h0cr);
 345
 346         usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 347         usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;       /*0*/
 348         usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 349         usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;    /*1*/
 350         usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 351         usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;         /*0*/
 352         usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 353         usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;          /*1*/
 354         usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 355         usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;          /*1*/
 356
 357         /* An 8-bit/60MHz interface is the only possible alternative
 358            when connecting the Device to the PHY */
 359         usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 360         usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;        /*1*/
 361
 362         /* To enable the USB 2.0 Device function through the UTMI interface */
 363         usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 364         usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;          /*1*/
 365
 366         sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 367         sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;                /*0*/
 368
 369         mtsdr(SDR0_PFC1, sdr0_pfc1);
 370         mtsdr(SDR0_USB2D0CR, usb2d0cr);
 371         mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 372         mtsdr(SDR0_USB2H0CR, usb2h0cr);
 373
 374         /*clear resets*/
 375         udelay(1000);
 376         mtsdr(SDR0_SRST1, 0x00000000);
 377         udelay(1000);
 378         mtsdr(SDR0_SRST0, 0x00000000);
 379
 380         printf("USB:   Host(int phy) Device(ext phy)\n");
 381
 382         return 0;
 383 }
 384
 385 #if defined(CONFIG_PCI)
 386 /*************************************************************************
 387  *  pci_pre_init
 388  *
 389  *  This routine is called just prior to registering the hose and gives
 390  *  the board the opportunity to check things. Returning a value of zero
 391  *  indicates that things are bad & PCI initialization should be aborted.
 392  *
 393  *      Different boards may wish to customize the pci controller structure
 394  *      (add regions, override default access routines, etc) or perform
 395  *      certain pre-initialization actions.
 396  *
 397  ************************************************************************/
 398 int pci_pre_init(struct pci_controller *hose)
 399 {
 400         unsigned long addr;
 401
 402         /*-------------------------------------------------------------------+
 403          * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
 404          * Workaround: Disable write pipelining to DDR SDRAM by setting
 405          * PLB0_ACR[WRP] = 0.
 406          *-------------------------------------------------------------------*/
 407
 408         /*-------------------------------------------------------------------+
 409           | Set priority for all PLB3 devices to 0.
 410           | Set PLB3 arbiter to fair mode.
 411           +-------------------------------------------------------------------*/
 412         mfsdr(sdr_amp1, addr);
 413         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 414         addr = mfdcr(plb3_acr);
 415         /* mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); */  /* ngngng */
 416         mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */
 417
 418         /*-------------------------------------------------------------------+
 419           | Set priority for all PLB4 devices to 0.
 420           +-------------------------------------------------------------------*/
 421         mfsdr(sdr_amp0, addr);
 422         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 423         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 424         /* mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); */  /* ngngng */
 425         mtdcr(plb4_acr, addr);  /* Sequoia */
 426
 427         /*-------------------------------------------------------------------+
 428           | Set Nebula PLB4 arbiter to fair mode.
 429           +-------------------------------------------------------------------*/
 430         /* Segment0 */
 431         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 432         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 433         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 434         /* addr = (addr & ~plb0_acr_wrp_mask); */  /* ngngng */
 435         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */
 436
 437         /* mtdcr(plb0_acr, addr); */ /* Sequoia */
 438         mtdcr(plb0_acr, 0);  /* PATCH HAB: WRITE PIPELINING OFF */
 439
 440         /* Segment1 */
 441         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 442         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 443         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 444         addr = (addr & ~plb1_acr_wrp_mask) ;
 445         /* mtdcr(plb1_acr, addr); */ /* Sequoia */
 446         mtdcr(plb1_acr, 0);  /* PATCH HAB: WRITE PIPELINING OFF */
 447
 448         return 1;
 449 }
 450
 451 /*************************************************************************
 452  *  pci_target_init
 453  *
 454  *      The bootstrap configuration provides default settings for the pci
 455  *      inbound map (PIM). But the bootstrap config choices are limited and
 456  *      may not be sufficient for a given board.
 457  *
 458  ************************************************************************/
 459 void pci_target_init(struct pci_controller *hose)
 460 {
 461         /*-------------------------------------------------------------+
 462          * Set up Direct MMIO registers
 463          *-------------------------------------------------------------*/
 464         /*-------------------------------------------------------------+
 465           | PowerPC440EPX PCI Master configuration.
 466           | Map one 1Gig range of PLB/processor addresses to PCI memory space.
 467           |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
 468           |               0xA0000000-0xDFFFFFFF
 469           |   Use byte reversed out routines to handle endianess.
 470           | Make this region non-prefetchable.
 471           +-------------------------------------------------------------*/
 472         /* PMM0 Mask/Attribute - disabled b4 setting */
 473         out32r(PCIX0_PMM0MA, 0x00000000);
 474         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 475         /* PMM0 PCI Low Address */
 476         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);
 477         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 478         /* 512M + No prefetching, and enable region */
 479         out32r(PCIX0_PMM0MA, 0xE0000001);
 480
 481         /* PMM0 Mask/Attribute - disabled b4 setting */
 482         out32r(PCIX0_PMM1MA, 0x00000000);
 483         out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 484         /* PMM0 PCI Low Address */
 485         out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);
 486         out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 487         /* 512M + No prefetching, and enable region */
 488         out32r(PCIX0_PMM1MA, 0xE0000001);
 489
 490         out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
 491         out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
 492         out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
 493         out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
 494
 495         /*------------------------------------------------------------------+
 496          * Set up Configuration registers
 497          *------------------------------------------------------------------*/
 498
 499         /* Program the board's subsystem id/vendor id */
 500         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 501                               CFG_PCI_SUBSYS_VENDORID);
 502         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 503
 504         /* Configure command register as bus master */
 505         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 506
 507         /* 240nS PCI clock */
 508         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 509
 510         /* No error reporting */
 511         pci_write_config_word(0, PCI_ERREN, 0);
 512
 513         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 514 }
 515
 516 /*************************************************************************
 517  *  pci_master_init
 518  *
 519  ************************************************************************/
 520 void pci_master_init(struct pci_controller *hose)
 521 {
 522         unsigned short temp_short;
 523
 524         /*---------------------------------------------------------------+
 525           | Write the PowerPC440 EP PCI Configuration regs.
 526           |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 527           |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 528           +--------------------------------------------------------------*/
 529         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 530         pci_write_config_word(0, PCI_COMMAND,
 531                               temp_short | PCI_COMMAND_MASTER |
 532                               PCI_COMMAND_MEMORY);
 533 }
 534
 535 /*************************************************************************
 536  *  is_pci_host
 537  *
 538  *      This routine is called to determine if a pci scan should be
 539  *      performed. With various hardware environments (especially cPCI and
 540  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 541  *      bit in the strap register, or generic host/adapter assumptions.
 542  *
 543  *      Rather than hard-code a bad assumption in the general 440 code, the
 544  *      440 pci code requires the board to decide at runtime.
 545  *
 546  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 547  *
 548  *
 549  ************************************************************************/
 550 int is_pci_host(struct pci_controller *hose)
 551 {
 552         return 1;
 553 }
 554 #endif   /* defined(CONFIG_PCI) */