board/netta2/netta2.c

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
  11  * U-Boot port on NetTA4 board
  12  */
  13
  14 #include <common.h>
  15 #include <miiphy.h>
  16
  17 #include "mpc8xx.h"
  18
  19 #ifdef CONFIG_HW_WATCHDOG
  20 #include <watchdog.h>
  21 #endif
  22
  23 int fec8xx_miiphy_read(char *devname, unsigned char addr,
  24                 unsigned char  reg, unsigned short *value);
  25 int fec8xx_miiphy_write(char *devname, unsigned char  addr,
  26                 unsigned char  reg, unsigned short value);
  27
  28 /****************************************************************/
  29
  30 /* some sane bit macros */
  31 #define _BD(_b)                         (1U << (31-(_b)))
  32 #define _BDR(_l, _h)                    (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
  33
  34 #define _BW(_b)                         (1U << (15-(_b)))
  35 #define _BWR(_l, _h)                    (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
  36
  37 #define _BB(_b)                         (1U << (7-(_b)))
  38 #define _BBR(_l, _h)                    (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
  39
  40 #define _B(_b)                          _BD(_b)
  41 #define _BR(_l, _h)                     _BDR(_l, _h)
  42
  43 /****************************************************************/
  44
  45 /*
  46  * Check Board Identity:
  47  *
  48  * Return 1 always.
  49  */
  50
  51 int checkboard(void)
  52 {
  53         printf ("Intracom NetTA2 V%d\n", CONFIG_NETTA2_VERSION);
  54         return (0);
  55 }
  56
  57 /****************************************************************/
  58
  59 #define _NOT_USED_      0xFFFFFFFF
  60
  61 /****************************************************************/
  62
  63 #define CS_0000         0x00000000
  64 #define CS_0001         0x10000000
  65 #define CS_0010         0x20000000
  66 #define CS_0011         0x30000000
  67 #define CS_0100         0x40000000
  68 #define CS_0101         0x50000000
  69 #define CS_0110         0x60000000
  70 #define CS_0111         0x70000000
  71 #define CS_1000         0x80000000
  72 #define CS_1001         0x90000000
  73 #define CS_1010         0xA0000000
  74 #define CS_1011         0xB0000000
  75 #define CS_1100         0xC0000000
  76 #define CS_1101         0xD0000000
  77 #define CS_1110         0xE0000000
  78 #define CS_1111         0xF0000000
  79
  80 #define BS_0000         0x00000000
  81 #define BS_0001         0x01000000
  82 #define BS_0010         0x02000000
  83 #define BS_0011         0x03000000
  84 #define BS_0100         0x04000000
  85 #define BS_0101         0x05000000
  86 #define BS_0110         0x06000000
  87 #define BS_0111         0x07000000
  88 #define BS_1000         0x08000000
  89 #define BS_1001         0x09000000
  90 #define BS_1010         0x0A000000
  91 #define BS_1011         0x0B000000
  92 #define BS_1100         0x0C000000
  93 #define BS_1101         0x0D000000
  94 #define BS_1110         0x0E000000
  95 #define BS_1111         0x0F000000
  96
  97 #define GPL0_AAAA       0x00000000
  98 #define GPL0_AAA0       0x00200000
  99 #define GPL0_AAA1       0x00300000
 100 #define GPL0_000A       0x00800000
 101 #define GPL0_0000       0x00A00000
 102 #define GPL0_0001       0x00B00000
 103 #define GPL0_111A       0x00C00000
 104 #define GPL0_1110       0x00E00000
 105 #define GPL0_1111       0x00F00000
 106
 107 #define GPL1_0000       0x00000000
 108 #define GPL1_0001       0x00040000
 109 #define GPL1_1110       0x00080000
 110 #define GPL1_1111       0x000C0000
 111
 112 #define GPL2_0000       0x00000000
 113 #define GPL2_0001       0x00010000
 114 #define GPL2_1110       0x00020000
 115 #define GPL2_1111       0x00030000
 116
 117 #define GPL3_0000       0x00000000
 118 #define GPL3_0001       0x00004000
 119 #define GPL3_1110       0x00008000
 120 #define GPL3_1111       0x0000C000
 121
 122 #define GPL4_0000       0x00000000
 123 #define GPL4_0001       0x00001000
 124 #define GPL4_1110       0x00002000
 125 #define GPL4_1111       0x00003000
 126
 127 #define GPL5_0000       0x00000000
 128 #define GPL5_0001       0x00000400
 129 #define GPL5_1110       0x00000800
 130 #define GPL5_1111       0x00000C00
 131 #define LOOP            0x00000080
 132
 133 #define EXEN            0x00000040
 134
 135 #define AMX_COL         0x00000000
 136 #define AMX_ROW         0x00000020
 137 #define AMX_MAR         0x00000030
 138
 139 #define NA              0x00000008
 140
 141 #define UTA             0x00000004
 142
 143 #define TODT            0x00000002
 144
 145 #define LAST            0x00000001
 146
 147 #define A10_AAAA        GPL0_AAAA
 148 #define A10_AAA0        GPL0_AAA0
 149 #define A10_AAA1        GPL0_AAA1
 150 #define A10_000A        GPL0_000A
 151 #define A10_0000        GPL0_0000
 152 #define A10_0001        GPL0_0001
 153 #define A10_111A        GPL0_111A
 154 #define A10_1110        GPL0_1110
 155 #define A10_1111        GPL0_1111
 156
 157 #define RAS_0000        GPL1_0000
 158 #define RAS_0001        GPL1_0001
 159 #define RAS_1110        GPL1_1110
 160 #define RAS_1111        GPL1_1111
 161
 162 #define CAS_0000        GPL2_0000
 163 #define CAS_0001        GPL2_0001
 164 #define CAS_1110        GPL2_1110
 165 #define CAS_1111        GPL2_1111
 166
 167 #define WE_0000         GPL3_0000
 168 #define WE_0001         GPL3_0001
 169 #define WE_1110         GPL3_1110
 170 #define WE_1111         GPL3_1111
 171
 172 /* #define CAS_LATENCY  3  */
 173 #define CAS_LATENCY     2
 174
 175 const uint sdram_table[0x40] = {
 176
 177 #if CAS_LATENCY == 3
 178         /* RSS */
 179         CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 180         CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 181         CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
 182         CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
 183         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 184         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
 185         _NOT_USED_, _NOT_USED_,
 186
 187         /* RBS */
 188         CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 189         CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 190         CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
 191         CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 192         CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 193         CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 194         CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,                         /* PALL  */
 195         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,           /* NOP   */
 196         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 197         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 198
 199         /* WSS */
 200         CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 201         CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 202         CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,                   /* WRITE */
 203         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
 204         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
 205         _NOT_USED_, _NOT_USED_, _NOT_USED_,
 206
 207         /* WBS */
 208         CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 209         CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 210         CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,                         /* WRITE */
 211         CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 212         CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 213         CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 214         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 215         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
 216         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
 217         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 218         _NOT_USED_, _NOT_USED_, _NOT_USED_,
 219 #endif
 220
 221 #if CAS_LATENCY == 2
 222         /* RSS */
 223         CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 224         CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 225         CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
 226         CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,                         /* NOP   */
 227         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
 228         _NOT_USED_,
 229         _NOT_USED_, _NOT_USED_,
 230
 231         /* RBS */
 232         CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 233         CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 234         CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
 235         CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 236         CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 237         CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 238         CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,                         /* NOP   */
 239         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
 240         _NOT_USED_,
 241         _NOT_USED_, _NOT_USED_, _NOT_USED_,
 242         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 243
 244         /* WSS */
 245         CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 246         CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,                         /* NOP   */
 247         CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA,                   /* WRITE */
 248         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
 249         _NOT_USED_,
 250         _NOT_USED_, _NOT_USED_,
 251         _NOT_USED_,
 252
 253         /* WBS */
 254         CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 255         CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,                         /* NOP   */
 256         CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL,                         /* WRITE */
 257         CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 258         CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 259         CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA,                   /* NOP   */
 260         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
 261         _NOT_USED_,
 262         _NOT_USED_, _NOT_USED_, _NOT_USED_,
 263         _NOT_USED_, _NOT_USED_, _NOT_USED_,
 264         _NOT_USED_, _NOT_USED_,
 265
 266 #endif
 267
 268         /* UPT */
 269         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP,            /* ATRFR */
 270         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 271         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 272         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 273         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP,            /* NOP   */
 274         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
 275         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 276         _NOT_USED_, _NOT_USED_,
 277
 278         /* EXC */
 279         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
 280         _NOT_USED_,
 281
 282         /* REG */
 283         CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
 284         CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
 285 };
 286
 287 #if CONFIG_NETTA2_VERSION == 2
 288 static const uint nandcs_table[0x40] = {
 289         /* RSS */
 290         CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
 291         CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
 292         CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
 293         CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
 294         CS_0000 | GPL4_0000 | GPL5_1111,
 295         CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
 296         CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
 297         CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,   /* NOP   */
 298
 299         /* RBS */
 300         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 301         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 302         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 303         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 304
 305         /* WSS */
 306         CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
 307         CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
 308         CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
 309         CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
 310         CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
 311         CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
 312         CS_0000 | GPL4_1111 | GPL5_1111,
 313         CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
 314
 315         /* WBS */
 316         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 317         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 318         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 319         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 320
 321         /* UPT */
 322         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 323         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 324         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 325
 326         /* EXC */
 327         CS_0001 | LAST,
 328         _NOT_USED_,
 329
 330         /* REG */
 331         CS_1110 ,
 332         CS_0001 | LAST,
 333 };
 334 #endif
 335
 336 /* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
 337 /* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
 338 #define MAR_SDRAM_INIT          ((CAS_LATENCY << 6) | 0x00000008LU)
 339
 340 /* 8 */
 341 #define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 342                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 343                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 344
 345 void check_ram(unsigned int addr, unsigned int size)
 346 {
 347         unsigned int i, j, v, vv;
 348         volatile unsigned int *p;
 349         unsigned int pv;
 350
 351         p = (unsigned int *)addr;
 352         pv = (unsigned int)p;
 353         for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
 354                 *p++ = pv;
 355
 356         p = (unsigned int *)addr;
 357         for (i = 0; i < size / sizeof(unsigned int); i++) {
 358                 v = (unsigned int)p;
 359                 vv = *p;
 360                 if (vv != v) {
 361                         printf("%p: read %08x instead of %08x\n", p, vv, v);
 362                         hang();
 363                 }
 364                 p++;
 365         }
 366
 367         for (j = 0; j < 5; j++) {
 368                 switch (j) {
 369                         case 0: v = 0x00000000; break;
 370                         case 1: v = 0xffffffff; break;
 371                         case 2: v = 0x55555555; break;
 372                         case 3: v = 0xaaaaaaaa; break;
 373                         default:v = 0xdeadbeef; break;
 374                 }
 375                 p = (unsigned int *)addr;
 376                 for (i = 0; i < size / sizeof(unsigned int); i++) {
 377                         *p = v;
 378                         vv = *p;
 379                         if (vv != v) {
 380                                 printf("%p: read %08x instead of %08x\n", p, vv, v);
 381                                 hang();
 382                         }
 383                         *p = ~v;
 384                         p++;
 385                 }
 386         }
 387 }
 388
 389 phys_size_t initdram(int board_type)
 390 {
 391         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 392         volatile memctl8xx_t *memctl = &immap->im_memctl;
 393         long int size;
 394
 395         upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
 396
 397         /*
 398          * Preliminary prescaler for refresh
 399          */
 400         memctl->memc_mptpr = MPTPR_PTP_DIV8;
 401
 402         memctl->memc_mar = MAR_SDRAM_INIT;      /* 32-bit address to be output on the address bus if AMX = 0b11 */
 403
 404         /*
 405          * Map controller bank 3 to the SDRAM bank at preliminary address.
 406          */
 407         memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
 408         memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 409
 410         memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE;       /* no refresh yet */
 411
 412         udelay(200);
 413
 414         /* perform SDRAM initialisation sequence */
 415         memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C);   /* precharge all                */
 416         udelay(1);
 417
 418         memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30);   /* refresh 2 times(0)           */
 419         udelay(1);
 420
 421         memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E);   /* exception program (write mar)*/
 422         udelay(1);
 423
 424         memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
 425
 426         udelay(10000);
 427
 428         {
 429                 u32 d1, d2;
 430
 431                 d1 = 0xAA55AA55;
 432                 *(volatile u32 *)0 = d1;
 433                 d2 = *(volatile u32 *)0;
 434                 if (d1 != d2) {
 435                         printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
 436                         hang();
 437                 }
 438
 439                 d1 = 0x55AA55AA;
 440                 *(volatile u32 *)0 = d1;
 441                 d2 = *(volatile u32 *)0;
 442                 if (d1 != d2) {
 443                         printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
 444                         hang();
 445                 }
 446         }
 447
 448         size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
 449
 450         if (size == 0) {
 451                 printf("SIZE is zero: LOOP on 0\n");
 452                 for (;;) {
 453                         *(volatile u32 *)0 = 0;
 454                         (void)*(volatile u32 *)0;
 455                 }
 456         }
 457
 458         return size;
 459 }
 460
 461 /* ------------------------------------------------------------------------- */
 462
 463 void reset_phys(void)
 464 {
 465         int phyno;
 466         unsigned short v;
 467
 468         udelay(10000);
 469         /* reset the damn phys */
 470         mii_init();
 471
 472         for (phyno = 0; phyno < 32; ++phyno) {
 473                 fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
 474                 if (v == 0xFFFF)
 475                         continue;
 476                 fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
 477                 udelay(10000);
 478                 fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
 479                                 BMCR_RESET | BMCR_ANENABLE);
 480                 udelay(10000);
 481         }
 482 }
 483
 484 /* ------------------------------------------------------------------------- */
 485
 486 /* GP = general purpose, SP = special purpose (on chip peripheral) */
 487
 488 /* bits that can have a special purpose or can be configured as inputs/outputs */
 489 #define PA_GP_INMASK    0
 490 #define PA_GP_OUTMASK   (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
 491 #define PA_SP_MASK      0
 492 #define PA_ODR_VAL      0
 493 #define PA_GP_OUTVAL    (_BW(3) | _BW(14) | _BW(15))
 494 #define PA_SP_DIRVAL    0
 495
 496 #define PB_GP_INMASK    _B(28)
 497 #define PB_GP_OUTMASK   (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
 498 #define PB_SP_MASK      (_BR(22, 25))
 499 #define PB_ODR_VAL      0
 500 #define PB_GP_OUTVAL    (_B(26) | _B(27) | _B(29) | _B(30))
 501 #define PB_SP_DIRVAL    0
 502
 503 #if CONFIG_NETTA2_VERSION == 1
 504 #define PC_GP_INMASK    _BW(12)
 505 #define PC_GP_OUTMASK   (_BW(10) | _BW(11) | _BW(13) | _BW(15))
 506 #elif CONFIG_NETTA2_VERSION == 2
 507 #define PC_GP_INMASK    (_BW(13) | _BW(15))
 508 #define PC_GP_OUTMASK   (_BW(10) | _BW(11) | _BW(12))
 509 #endif
 510 #define PC_SP_MASK      0
 511 #define PC_SOVAL        0
 512 #define PC_INTVAL       0
 513 #define PC_GP_OUTVAL    (_BW(10) | _BW(11))
 514 #define PC_SP_DIRVAL    0
 515
 516 #if CONFIG_NETTA2_VERSION == 1
 517 #define PE_GP_INMASK    _B(31)
 518 #define PE_GP_OUTMASK   (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
 519 #define PE_GP_OUTVAL    (_B(20) | _B(24) | _B(27) | _B(28))
 520 #elif CONFIG_NETTA2_VERSION == 2
 521 #define PE_GP_INMASK    _BR(28, 31)
 522 #define PE_GP_OUTMASK   (_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
 523 #define PE_GP_OUTVAL    (_B(20) | _B(24) | _B(27))
 524 #endif
 525 #define PE_SP_MASK      0
 526 #define PE_ODR_VAL      0
 527 #define PE_SP_DIRVAL    0
 528
 529 int board_early_init_f(void)
 530 {
 531         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 532         volatile iop8xx_t *ioport = &immap->im_ioport;
 533         volatile cpm8xx_t *cpm = &immap->im_cpm;
 534         volatile memctl8xx_t *memctl = &immap->im_memctl;
 535
 536         /* NAND chip select */
 537 #if CONFIG_NETTA2_VERSION == 1
 538         memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
 539         memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
 540 #elif CONFIG_NETTA2_VERSION == 2
 541         upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
 542         memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
 543         memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);
 544         memctl->memc_mamr = 0;  /* all clear */
 545 #endif
 546
 547         /* DSP chip select */
 548         memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
 549         memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
 550
 551 #if CONFIG_NETTA2_VERSION == 1
 552         memctl->memc_br4 &= ~BR_V;
 553 #endif
 554         memctl->memc_br5 &= ~BR_V;
 555         memctl->memc_br6 &= ~BR_V;
 556         memctl->memc_br7 &= ~BR_V;
 557
 558         ioport->iop_padat       = PA_GP_OUTVAL;
 559         ioport->iop_paodr       = PA_ODR_VAL;
 560         ioport->iop_padir       = PA_GP_OUTMASK | PA_SP_DIRVAL;
 561         ioport->iop_papar       = PA_SP_MASK;
 562
 563         cpm->cp_pbdat           = PB_GP_OUTVAL;
 564         cpm->cp_pbodr           = PB_ODR_VAL;
 565         cpm->cp_pbdir           = PB_GP_OUTMASK | PB_SP_DIRVAL;
 566         cpm->cp_pbpar           = PB_SP_MASK;
 567
 568         ioport->iop_pcdat       = PC_GP_OUTVAL;
 569         ioport->iop_pcdir       = PC_GP_OUTMASK | PC_SP_DIRVAL;
 570         ioport->iop_pcso        = PC_SOVAL;
 571         ioport->iop_pcint       = PC_INTVAL;
 572         ioport->iop_pcpar       = PC_SP_MASK;
 573
 574         cpm->cp_pedat           = PE_GP_OUTVAL;
 575         cpm->cp_peodr           = PE_ODR_VAL;
 576         cpm->cp_pedir           = PE_GP_OUTMASK | PE_SP_DIRVAL;
 577         cpm->cp_pepar           = PE_SP_MASK;
 578
 579         return 0;
 580 }
 581
 582 #ifdef CONFIG_HW_WATCHDOG
 583
 584 void hw_watchdog_reset(void)
 585 {
 586         /* XXX add here the really funky stuff */
 587 }
 588
 589 #endif
 590
 591 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 592 int overwrite_console(void)
 593 {
 594         /* printf("overwrite_console called\n"); */
 595         return 0;
 596 }
 597 #endif
 598
 599 extern int drv_phone_init(void);
 600 extern int drv_phone_use_me(void);
 601 extern int drv_phone_is_idle(void);
 602
 603 int misc_init_r(void)
 604 {
 605         return 0;
 606 }
 607
 608 int last_stage_init(void)
 609 {
 610 #if CONFIG_NETTA2_VERSION == 2
 611         int i;
 612 #endif
 613
 614 #if CONFIG_NETTA2_VERSION == 2
 615         /* assert peripheral reset */
 616         ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
 617         for (i = 0; i < 10; i++)
 618                 udelay(1000);
 619         ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |=  _BW(12);
 620 #endif
 621         reset_phys();
 622
 623         return 0;
 624 }