board/nvidia/common/board.c

   1 /*
   2  *  (C) Copyright 2010,2011
   3  *  NVIDIA Corporation <www.nvidia.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <ns16550.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/tegra2.h>
  28 #include <asm/arch/sys_proto.h>
  29
  30 #include <asm/arch/clk_rst.h>
  31 #include <asm/arch/pinmux.h>
  32 #include <asm/arch/uart.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 const struct tegra2_sysinfo sysinfo = {
  37         CONFIG_TEGRA2_BOARD_STRING
  38 };
  39
  40 /*
  41  * Routine: timer_init
  42  * Description: init the timestamp and lastinc value
  43  */
  44 int timer_init(void)
  45 {
  46         reset_timer();
  47         return 0;
  48 }
  49
  50 /*
  51  * Routine: clock_init_uart
  52  * Description: init the PLL and clock for the UART(s)
  53  */
  54 static void clock_init_uart(void)
  55 {
  56         struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  57         static int pllp_init_done;
  58         u32 reg;
  59
  60         if (!pllp_init_done) {
  61                 /* Override pllp setup for 216MHz operation. */
  62                 reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP);
  63                 reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM);
  64                 writel(reg, &clkrst->crc_pllp_base);
  65
  66                 reg |= PLL_ENABLE;
  67                 writel(reg, &clkrst->crc_pllp_base);
  68
  69                 reg &= ~PLL_BYPASS;
  70                 writel(reg, &clkrst->crc_pllp_base);
  71
  72                 pllp_init_done++;
  73         }
  74
  75         /* Now do the UART reset/clock enable */
  76 #if defined(CONFIG_TEGRA2_ENABLE_UARTA)
  77         /* Assert Reset to UART */
  78         reg = readl(&clkrst->crc_rst_dev_l);
  79         reg |= SWR_UARTA_RST;           /* SWR_UARTA_RST = 1 */
  80         writel(reg, &clkrst->crc_rst_dev_l);
  81
  82         /* Enable clk to UART */
  83         reg = readl(&clkrst->crc_clk_out_enb_l);
  84         reg |= CLK_ENB_UARTA;           /* CLK_ENB_UARTA = 1 */
  85         writel(reg, &clkrst->crc_clk_out_enb_l);
  86
  87         /* Enable pllp_out0 to UART */
  88         reg = readl(&clkrst->crc_clk_src_uarta);
  89         reg &= 0x3FFFFFFF;      /* UARTA_CLK_SRC = 00, PLLP_OUT0 */
  90         writel(reg, &clkrst->crc_clk_src_uarta);
  91
  92         /* wait for 2us */
  93         udelay(2);
  94
  95         /* De-assert reset to UART */
  96         reg = readl(&clkrst->crc_rst_dev_l);
  97         reg &= ~SWR_UARTA_RST;          /* SWR_UARTA_RST = 0 */
  98         writel(reg, &clkrst->crc_rst_dev_l);
  99 #endif  /* CONFIG_TEGRA2_ENABLE_UARTA */
 100 #if defined(CONFIG_TEGRA2_ENABLE_UARTD)
 101         /* Assert Reset to UART */
 102         reg = readl(&clkrst->crc_rst_dev_u);
 103         reg |= SWR_UARTD_RST;           /* SWR_UARTD_RST = 1 */
 104         writel(reg, &clkrst->crc_rst_dev_u);
 105
 106         /* Enable clk to UART */
 107         reg = readl(&clkrst->crc_clk_out_enb_u);
 108         reg |= CLK_ENB_UARTD;           /* CLK_ENB_UARTD = 1 */
 109         writel(reg, &clkrst->crc_clk_out_enb_u);
 110
 111         /* Enable pllp_out0 to UART */
 112         reg = readl(&clkrst->crc_clk_src_uartd);
 113         reg &= 0x3FFFFFFF;      /* UARTD_CLK_SRC = 00, PLLP_OUT0 */
 114         writel(reg, &clkrst->crc_clk_src_uartd);
 115
 116         /* wait for 2us */
 117         udelay(2);
 118
 119         /* De-assert reset to UART */
 120         reg = readl(&clkrst->crc_rst_dev_u);
 121         reg &= ~SWR_UARTD_RST;          /* SWR_UARTD_RST = 0 */
 122         writel(reg, &clkrst->crc_rst_dev_u);
 123 #endif  /* CONFIG_TEGRA2_ENABLE_UARTD */
 124 }
 125
 126 /*
 127  * Routine: pin_mux_uart
 128  * Description: setup the pin muxes/tristate values for the UART(s)
 129  */
 130 static void pin_mux_uart(void)
 131 {
 132         struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
 133         u32 reg;
 134
 135 #if defined(CONFIG_TEGRA2_ENABLE_UARTA)
 136         reg = readl(&pmt->pmt_ctl_c);
 137         reg &= 0xFFF0FFFF;      /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
 138         writel(reg, &pmt->pmt_ctl_c);
 139
 140         reg = readl(&pmt->pmt_tri_a);
 141         reg &= ~Z_IRRX;         /* Z_IRRX = normal (0) */
 142         reg &= ~Z_IRTX;         /* Z_IRTX = normal (0) */
 143         writel(reg, &pmt->pmt_tri_a);
 144 #endif  /* CONFIG_TEGRA2_ENABLE_UARTA */
 145 #if defined(CONFIG_TEGRA2_ENABLE_UARTD)
 146         reg = readl(&pmt->pmt_ctl_b);
 147         reg &= 0xFFFFFFF3;      /* GMC_SEL [3:2] = 00, UARTD */
 148         writel(reg, &pmt->pmt_ctl_b);
 149
 150         reg = readl(&pmt->pmt_tri_a);
 151         reg &= ~Z_GMC;          /* Z_GMC = normal (0) */
 152         writel(reg, &pmt->pmt_tri_a);
 153 #endif  /* CONFIG_TEGRA2_ENABLE_UARTD */
 154 }
 155
 156 /*
 157  * Routine: clock_init
 158  * Description: Do individual peripheral clock reset/enables
 159  */
 160 void clock_init(void)
 161 {
 162         clock_init_uart();
 163 }
 164
 165 /*
 166  * Routine: pinmux_init
 167  * Description: Do individual peripheral pinmux configs
 168  */
 169 void pinmux_init(void)
 170 {
 171         pin_mux_uart();
 172 }
 173
 174 /*
 175  * Routine: board_init
 176  * Description: Early hardware init.
 177  */
 178 int board_init(void)
 179 {
 180         /* boot param addr */
 181         gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
 182         /* board id for Linux */
 183         gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
 184
 185         /* Initialize peripheral clocks */
 186         clock_init();
 187
 188         /* Initialize periph pinmuxes */
 189         pinmux_init();
 190
 191         return 0;
 192 }