board/nvidia/seaboard/seaboard.c

   1 /*
   2  *  (C) Copyright 2010,2011
   3  *  NVIDIA Corporation <www.nvidia.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/tegra.h>
  11 #include <asm/arch-tegra/board.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/funcmux.h>
  14 #include <asm/arch/gpio.h>
  15 #include <asm/arch/pinmux.h>
  16 #include <asm/gpio.h>
  17
  18 /* TODO: Remove this code when the SPI switch is working */
  19 #if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA)
  20 void gpio_early_init_uart(void)
  21 {
  22         /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
  23         gpio_request(TEGRA_GPIO(I, 3), "uart_en");
  24         gpio_direction_output(TEGRA_GPIO(I, 3), 0);
  25 }
  26 #endif
  27
  28 #ifdef CONFIG_MMC_SDHCI_TEGRA
  29 /*
  30  * Routine: pin_mux_mmc
  31  * Description: setup the pin muxes/tristate values for the SDMMC(s)
  32  */
  33 void pin_mux_mmc(void)
  34 {
  35         funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
  36         funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT);
  37
  38         /* For power GPIO PI6 */
  39         pinmux_tristate_disable(PMUX_PINGRP_ATA);
  40         /* For CD GPIO PI5 */
  41         pinmux_tristate_disable(PMUX_PINGRP_ATC);
  42 }
  43 #endif
  44
  45 void pin_mux_usb(void)
  46 {
  47         /* For USB0's GPIO PD0. For now, since we have no pinmux in fdt */
  48         pinmux_tristate_disable(PMUX_PINGRP_SLXK);
  49         /* For USB1's ULPI signals */
  50         funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
  51         pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
  52         pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
  53         /* USB1 PHY reset GPIO */
  54         pinmux_tristate_disable(PMUX_PINGRP_UAC);
  55 }