board/o2dnt/o2dnt.c

   1 /*
   2  * (C) Copyright 2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <mpc5xxx.h>
  29 #include <pci.h>
  30 #include <netdev.h>
  31
  32 #define SDRAM_MODE      0x00CD0000
  33 #define SDRAM_CONTROL   0x504F0000
  34 #define SDRAM_CONFIG1   0xD2322800
  35 #define SDRAM_CONFIG2   0x8AD70000
  36
  37 static void sdram_start (int hi_addr)
  38 {
  39         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  40
  41         /* unlock mode register */
  42         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  43         __asm__ volatile ("sync");
  44
  45         /* precharge all banks */
  46         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  47         __asm__ volatile ("sync");
  48
  49         /* precharge all banks */
  50         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  51         __asm__ volatile ("sync");
  52
  53         /* auto refresh */
  54         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
  55         __asm__ volatile ("sync");
  56
  57         /* set mode register */
  58         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  59         __asm__ volatile ("sync");
  60
  61         /* normal operation */
  62         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  63         __asm__ volatile ("sync");
  64 }
  65
  66 /*
  67  * ATTENTION: Although partially referenced initdram does NOT make real use
  68  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  69  *            is something else than 0x00000000.
  70  */
  71 phys_size_t initdram (int board_type)
  72 {
  73         ulong dramsize = 0;
  74         ulong dramsize2 = 0;
  75         ulong test1, test2;
  76
  77         /* setup SDRAM chip selects */
  78         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
  79         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
  80         __asm__ volatile ("sync");
  81
  82         /* setup config registers */
  83         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
  84         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
  85         __asm__ volatile ("sync");
  86
  87         /* find RAM size using SDRAM CS0 only */
  88         sdram_start(0);
  89         test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
  90         sdram_start(1);
  91         test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
  92         if (test1 > test2) {
  93                 sdram_start(0);
  94                 dramsize = test1;
  95         } else {
  96                 dramsize = test2;
  97         }
  98
  99         /* memory smaller than 1MB is impossible */
 100         if (dramsize < (1 << 20)) {
 101                 dramsize = 0;
 102         }
 103
 104         /* set SDRAM CS0 size according to the amount of RAM found */
 105         if (dramsize > 0)
 106                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
 107         else
 108                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 109
 110         /* let SDRAM CS1 start right after CS0 */
 111         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
 112
 113         /* find RAM size using SDRAM CS1 only */
 114         if (!dramsize)
 115                 sdram_start(0);
 116
 117         test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 118
 119         if (!dramsize) {
 120                 sdram_start(1);
 121                 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 122         }
 123
 124         if (test1 > test2) {
 125                 sdram_start(0);
 126                 dramsize2 = test1;
 127         } else {
 128                 dramsize2 = test2;
 129         }
 130
 131         /* memory smaller than 1MB is impossible */
 132         if (dramsize2 < (1 << 20))
 133                 dramsize2 = 0;
 134
 135         /* set SDRAM CS1 size according to the amount of RAM found */
 136         if (dramsize2 > 0) {
 137                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 138                         | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 139         } else {
 140                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 141         }
 142
 143         return dramsize + dramsize2;
 144 }
 145
 146 int checkboard (void)
 147 {
 148         puts ("Board: O2DNT\n");
 149         return 0;
 150 }
 151
 152 void flash_preinit(void)
 153 {
 154         /*
 155          * Now, when we are in RAM, enable flash write
 156          * access for detection process.
 157          * Note that CS_BOOT cannot be cleared when
 158          * executing in flash.
 159          */
 160         *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 161 }
 162
 163 void flash_afterinit(ulong size)
 164 {
 165         if (size == 0x800000) { /* adjust mapping */
 166                 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
 167                         START_REG(CONFIG_SYS_BOOTCS_START | size);
 168
 169                 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 170                         STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
 171         }
 172 }
 173
 174 #ifdef  CONFIG_PCI
 175 static struct pci_controller hose;
 176
 177 extern void pci_mpc5xxx_init(struct pci_controller *);
 178
 179 void pci_init_board(void)
 180 {
 181         pci_mpc5xxx_init(&hose);
 182 }
 183 #endif
 184
 185 int board_eth_init(bd_t *bis)
 186 {
 187         cpu_eth_init(bis); /* Built in FEC comes first */
 188         return pci_eth_init(bis);
 189 }