board/omap1510inn/platform.S

   1 /*
   2  * Board specific setup info
   3  *
   4  * (C) Copyright 2003
   5  * Texas Instruments, <www.ti.com>
   6  *
   7  * -- Some bits of code used from rrload's head_OMAP1510.s --
   8  * Copyright (C) 2002 RidgeRun, Inc.
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <config.h>
  30 #include <version.h>
  31
  32 #if defined(CONFIG_OMAP1510)
  33 #include <./configs/omap1510.h>
  34 #endif
  35
  36 #define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
  37
  38
  39 _TEXT_BASE:
  40         .word   TEXT_BASE        /* sdram load addr from config.mk */
  41
  42 .globl platformsetup
  43 platformsetup:
  44
  45         /*
  46          * Configure 1510 pins functions to match our board.
  47          */
  48         ldr     r0, REG_PULL_DWN_CTRL_0
  49         ldr     r1, VAL_PULL_DWN_CTRL_0
  50         str     r1, [r0]
  51         ldr     r0, REG_PULL_DWN_CTRL_1
  52         ldr     r1, VAL_PULL_DWN_CTRL_1
  53         str     r1, [r0]
  54         ldr     r0, REG_PULL_DWN_CTRL_2
  55         ldr     r1, VAL_PULL_DWN_CTRL_2
  56         str     r1, [r0]
  57         ldr     r0, REG_PULL_DWN_CTRL_3
  58         ldr     r1, VAL_PULL_DWN_CTRL_3
  59         str     r1, [r0]
  60         ldr     r0, REG_FUNC_MUX_CTRL_4
  61         ldr     r1, VAL_FUNC_MUX_CTRL_4
  62         str     r1, [r0]
  63         ldr     r0, REG_FUNC_MUX_CTRL_5
  64         ldr     r1, VAL_FUNC_MUX_CTRL_5
  65         str     r1, [r0]
  66         ldr     r0, REG_FUNC_MUX_CTRL_6
  67         ldr     r1, VAL_FUNC_MUX_CTRL_6
  68         str     r1, [r0]
  69         ldr     r0, REG_FUNC_MUX_CTRL_7
  70         ldr     r1, VAL_FUNC_MUX_CTRL_7
  71         str     r1, [r0]
  72         ldr     r0, REG_FUNC_MUX_CTRL_8
  73         ldr     r1, VAL_FUNC_MUX_CTRL_8
  74         str     r1, [r0]
  75         ldr     r0, REG_FUNC_MUX_CTRL_9
  76         ldr     r1, VAL_FUNC_MUX_CTRL_9
  77         str     r1, [r0]
  78         ldr     r0, REG_FUNC_MUX_CTRL_A
  79         ldr     r1, VAL_FUNC_MUX_CTRL_A
  80         str     r1, [r0]
  81         ldr     r0, REG_FUNC_MUX_CTRL_B
  82         ldr     r1, VAL_FUNC_MUX_CTRL_B
  83         str     r1, [r0]
  84         ldr     r0, REG_FUNC_MUX_CTRL_C
  85         ldr     r1, VAL_FUNC_MUX_CTRL_C
  86         str     r1, [r0]
  87         ldr     r0, REG_VOLTAGE_CTRL_0
  88         ldr     r1, VAL_VOLTAGE_CTRL_0
  89         str     r1, [r0]
  90         ldr     r0, REG_TEST_DBG_CTRL_0
  91         ldr     r1, VAL_TEST_DBG_CTRL_0
  92         str     r1, [r0]
  93         ldr     r0, REG_MOD_CONF_CTRL_0
  94         ldr     r1, VAL_MOD_CONF_CTRL_0
  95         str     r1, [r0]
  96
  97         /* Move to 1510 mode */
  98         ldr     r0, REG_COMP_MODE_CTRL_0
  99         ldr     r1, VAL_COMP_MODE_CTRL_0
 100         str     r1, [r0]
 101
 102         /* Set up Traffic Ctlr*/
 103         ldr r0, REG_TC_IMIF_PRIO
 104         mov r1, #0x0
 105         str r1, [r0]
 106         ldr r0, REG_TC_EMIFS_PRIO
 107         str r1, [r0]
 108         ldr r0, REG_TC_EMIFF_PRIO
 109         str r1, [r0]
 110
 111         ldr r0, REG_TC_EMIFS_CONFIG
 112         ldr r1, [r0]
 113         bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
 114         bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
 115         str r1, [r0]        /* EMIFS GlB Configuration. (value 0x12 most likely) */
 116
 117         /* Setup some clock domains */
 118         ldr r1, =OMAP1510_CLKS
 119         ldr r0, REG_ARM_IDLECT2
 120         strh r1, [r0]  /* CLKM, Clock domain control. */
 121
 122         mov r1, #0x01  /* PER_EN bit */
 123         ldr r0, REG_ARM_RSTCT2
 124         strh r1, [r0]  /* CLKM; Peripheral reset. */
 125
 126         /* Set CLKM to Sync-Scalable  */
 127         /* I supposidly need to enable the dsp clock before switching */
 128         mov r1, #0x1000
 129         ldr r0, REG_ARM_SYSST
 130         strh r1, [r0]
 131         mov r0, #0x400
 132 1:
 133         subs r0, r0, #0x1   /* wait for any bubbles to finish */
 134         bne 1b
 135
 136         ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
 137         ldr r0, REG_ARM_CKCTL
 138         strh r1, [r0]
 139
 140         /* setup DPLL 1 */
 141         ldr r1, VAL_DPLL1_CTL
 142         ldr r0, REG_DPLL1_CTL
 143         strh r1, [r0]
 144         ands r1, r1, #0x10  /* Check if PLL is enabled. */
 145         beq lock_end        /* Do not look for lock if BYPASS selected */
 146 2:
 147         ldrh r1, [r0]
 148         ands r1, r1, #0x01  /* Check the LOCK bit. */
 149         beq 2b              /* ...loop until bit goes hi. */
 150 lock_end:
 151
 152         /* Set memory timings corresponding to the new clock speed */
 153
 154         /* Check execution location to determine current execution location
 155          * and branch to appropriate initialization code.
 156          */
 157         mov r0, #0x10000000                 /* Load physical SDRAM base. */
 158         mov r1, pc                          /* Get current execution location. */
 159         cmp r1, r0                          /* Compare. */
 160         bge skip_sdram                      /* Skip over EMIF-fast initialization if running from SDRAM. */
 161
 162         /*
 163          * Delay for SDRAM initialization.
 164          */
 165         mov r3, #0x1800                        /* value should be checked */
 166 3:
 167         subs r3, r3, #0x1                     /* Decrement count */
 168         bne 3b
 169
 170         /*
 171          * Set SDRAM control values. Disable refresh before MRS command.
 172          */
 173         ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
 174         bic r3, r0, #0xC                    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
 175         orr r3, r3, #0x8000000              /* (BIT27) Disable CLK when Power down or Self-Refresh */
 176         orr r3, r3, #0x4000000              /* BIT26 Power Down Enable */
 177         ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
 178         str r3, [r2]                        /* Store the passed value with AR disabled. */
 179
 180         ldr r1, VAL_TC_EMIFF_MRS            /* get MRS value */
 181         ldr r2, REG_TC_EMIFF_MRS            /* Point to MRS register. */
 182         str r1, [r2]                        /* Store the passed value.*/
 183
 184         ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
 185         str r0, [r2]                        /* Store the passed value. */
 186
 187         /*
 188          * Delay for SDRAM initialization.
 189          */
 190         mov r3, #0x1800
 191 4:
 192         subs r3, r3, #1                     /* Decrement count. */
 193         bne 4b
 194
 195 skip_sdram:
 196
 197         /* slow interface */
 198         ldr r1, VAL_TC_EMIFS_CS0_CONFIG
 199         ldr r0, REG_TC_EMIFS_CS0_CONFIG
 200         str r1, [r0] /* Chip Select 0 */
 201         ldr r1, VAL_TC_EMIFS_CS1_CONFIG
 202         ldr r0, REG_TC_EMIFS_CS1_CONFIG
 203         str r1, [r0] /* Chip Select 1 */
 204         ldr r1, VAL_TC_EMIFS_CS2_CONFIG
 205         ldr r0, REG_TC_EMIFS_CS2_CONFIG
 206         str r1, [r0] /* Chip Select 2 */
 207         ldr r1, VAL_TC_EMIFS_CS3_CONFIG
 208         ldr r0, REG_TC_EMIFS_CS3_CONFIG
 209         str r1, [r0] /* Chip Select 3 */
 210
 211  /* Next, Enable the RS232 Line Drivers in the FPGA. */
 212  /* Also, power on the audio CODEC's amplifier here, */
 213  /* which will make a noise on the audio output. */
 214  /* This is done here instead of in the kernel so there */
 215  /* isn't a loud popping noise at the start of each */
 216  /* song. */
 217  /* Also, disable the CODEC's clocks. */
 218  /* omap1510-HelenP1 [specific] */
 219
 220         ldr r0, REG_FPGA_POWER
 221         mov r1, #0
 222         ldr r2, REG_FPGA_DIP_SWITCH
 223         ldrb r3, [r2]
 224         cmp r3, #0x8
 225         movne r1, #0x62     /* Enable the RS232 Line Drivers in the EPLD */
 226         strb r1, [r0]
 227         ldr r0, REG_FPGA_AUDIO
 228         mov r1, #0x0     /* Disable sound driver (CODEC clocks) */
 229         strb r1, [r0]
 230
 231         /* back to arch calling code */
 232         mov     pc, lr
 233
 234 /* the literal pools origin */
 235         .ltorg
 236
 237 /* OMAP configuration registers */
 238 REG_FUNC_MUX_CTRL_0:            /* 32 bits */
 239         .word 0xfffe1000
 240 REG_FUNC_MUX_CTRL_1:            /* 32 bits */
 241         .word 0xfffe1004
 242 REG_FUNC_MUX_CTRL_2:            /* 32 bits */
 243         .word 0xfffe1008
 244 REG_COMP_MODE_CTRL_0:           /* 32 bits */
 245         .word 0xfffe100c
 246 REG_FUNC_MUX_CTRL_3:            /* 32 bits */
 247         .word 0xfffe1010
 248 REG_FUNC_MUX_CTRL_4:            /* 32 bits */
 249         .word 0xfffe1014
 250 REG_FUNC_MUX_CTRL_5:            /* 32 bits */
 251         .word 0xfffe1018
 252 REG_FUNC_MUX_CTRL_6:            /* 32 bits */
 253         .word 0xfffe101c
 254 REG_FUNC_MUX_CTRL_7:            /* 32 bits */
 255         .word 0xfffe1020
 256 REG_FUNC_MUX_CTRL_8:            /* 32 bits */
 257         .word 0xfffe1024
 258 REG_FUNC_MUX_CTRL_9:            /* 32 bits */
 259         .word 0xfffe1028
 260 REG_FUNC_MUX_CTRL_A:            /* 32 bits */
 261         .word 0xfffe102C
 262 REG_FUNC_MUX_CTRL_B:            /* 32 bits */
 263         .word 0xfffe1030
 264 REG_FUNC_MUX_CTRL_C:            /* 32 bits */
 265         .word 0xfffe1034
 266 REG_FUNC_MUX_CTRL_D:            /* 32 bits */
 267         .word 0xfffe1038
 268 REG_PULL_DWN_CTRL_0:            /* 32 bits */
 269         .word 0xfffe1040
 270 REG_PULL_DWN_CTRL_1:            /* 32 bits */
 271         .word 0xfffe1044
 272 REG_PULL_DWN_CTRL_2:            /* 32 bits */
 273         .word 0xfffe1048
 274 REG_PULL_DWN_CTRL_3:            /* 32 bits */
 275         .word 0xfffe104c
 276 REG_VOLTAGE_CTRL_0:             /* 32 bits */
 277         .word 0xfffe1060
 278 REG_TEST_DBG_CTRL_0:            /* 32 bits */
 279         .word 0xfffe1070
 280 REG_MOD_CONF_CTRL_0:            /* 32 bits */
 281         .word 0xfffe1080
 282 REG_TC_IMIF_PRIO:               /* 32 bits */
 283         .word 0xfffecc00
 284 REG_TC_EMIFS_PRIO:              /* 32 bits */
 285         .word 0xfffecc04
 286 REG_TC_EMIFF_PRIO:              /* 32 bits */
 287         .word 0xfffecc08
 288 REG_TC_EMIFS_CONFIG:            /* 32 bits */
 289         .word 0xfffecc0c
 290 REG_TC_EMIFS_CS0_CONFIG:        /* 32 bits */
 291         .word 0xfffecc10
 292 REG_TC_EMIFS_CS1_CONFIG:        /* 32 bits */
 293         .word 0xfffecc14
 294 REG_TC_EMIFS_CS2_CONFIG:        /* 32 bits */
 295         .word 0xfffecc18
 296 REG_TC_EMIFS_CS3_CONFIG:        /* 32 bits */
 297         .word 0xfffecc1c
 298 REG_TC_EMIFF_SDRAM_CONFIG:      /* 32 bits */
 299         .word 0xfffecc20
 300 REG_TC_EMIFF_MRS:               /* 32 bits */
 301         .word 0xfffecc24
 302 /* MPU clock/reset/power mode control registers */
 303 REG_ARM_CKCTL:                  /* 16 bits */
 304         .word 0xfffece00
 305 REG_ARM_IDLECT2:                /* 16 bits */
 306         .word 0xfffece08
 307 REG_ARM_RSTCT2:                 /* 16 bits */
 308         .word 0xfffece14
 309 REG_ARM_SYSST:                  /* 16 bits */
 310         .word 0xfffece18
 311 /* DPLL control registers */
 312 REG_DPLL1_CTL:                  /* 16 bits */
 313         .word 0xfffecf00
 314 /* identification code register */
 315 REG_IDCODE:                     /* 32 bits */
 316         .word 0xfffed404
 317
 318 /* Innovator specific */
 319 REG_FPGA_LED_DIGIT:             /* 8 bits (not used on Innovator) */
 320         .word 0x08000003
 321 REG_FPGA_POWER:                 /* 8 bits */
 322         .word 0x08000005
 323 REG_FPGA_AUDIO:                 /* 8 bits (not used on Innovator) */
 324         .word 0x0800000c
 325 REG_FPGA_DIP_SWITCH:            /* 8 bits (not used on Innovator) */
 326         .word 0x0800000e
 327
 328 VAL_COMP_MODE_CTRL_0:
 329         .word 0x0000eaef
 330 VAL_FUNC_MUX_CTRL_4:
 331         .word 0x00000000
 332 VAL_FUNC_MUX_CTRL_5:
 333         .word 0x00000000
 334 VAL_FUNC_MUX_CTRL_6:
 335         .word 0x00000001
 336 VAL_FUNC_MUX_CTRL_7:
 337         .word 0x00000000
 338 VAL_FUNC_MUX_CTRL_8:
 339         .word 0x10001200
 340 VAL_FUNC_MUX_CTRL_9:
 341         .word 0x01201012
 342 VAL_FUNC_MUX_CTRL_A:
 343         .word 0x00000248
 344 VAL_FUNC_MUX_CTRL_B:
 345         .word 0x00000248
 346 VAL_FUNC_MUX_CTRL_C:
 347         .word 0x09000000
 348 VAL_FUNC_MUX_CTRL_D:
 349         .word 0x00000000
 350 VAL_PULL_DWN_CTRL_0:
 351         .word 0x11a10000
 352 VAL_PULL_DWN_CTRL_1:
 353         .word 0x2e047fff
 354 VAL_PULL_DWN_CTRL_2:
 355         .word 0xffd7d3e6
 356 VAL_PULL_DWN_CTRL_3:
 357         .word 0x00003f03
 358 VAL_VOLTAGE_CTRL_0:
 359         .word 0x00000007
 360 VAL_TEST_DBG_CTRL_0:
 361         /*  See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 .
 362          *   This slows down internal SRAM accesses.
 363          */
 364         .word 0x00000007
 365 VAL_MOD_CONF_CTRL_0:
 366         .word 0x0b000008
 367 VAL_ARM_CKCTL:
 368         .word 0x010f
 369 VAL_DPLL1_CTL:
 370         .word 0x2710
 371 VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
 372         .word 0x00001149
 373 VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
 374         .word 0x00004158
 375 VAL_TC_EMIFS_CS0_CONFIG:
 376         .word 0x002130b0
 377 VAL_TC_EMIFS_CS1_CONFIG:
 378         .word 0x0000f559
 379 VAL_TC_EMIFS_CS2_CONFIG:
 380         .word 0x000055f0
 381 VAL_TC_EMIFS_CS3_CONFIG:
 382         .word 0x00003331
 383 VAL_TC_EMIFF_SDRAM_CONFIG:
 384         .word 0x010290fc
 385 VAL_TC_EMIFF_MRS:
 386         .word 0x00000027